SC18IM700IPW datasheet(16/22 Pages) NXP

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SC18IM700_2

Product data sheet

Rev. 02 — 10 August 2007

16 of 22

NXP Semiconductors

SC18IM700

Master I2C-bus controller with UART interface

12. Dynamic characteristics

Table 12.

I2C-bus timing characteristics

All the timing limits are valid within the operating supply voltage and ambient temperature range; VDD = 2.4 V to 3.6 V;

Tamb = −40 °C to +85 °C; and refer to VIL and VIH with an input voltage of VSS to VDD.

Symbol

Parameter

Conditions

Standard mode

I2C-bus

Fast mode

I2C-bus

Unit

Min

Max

Min

Max

fSCL

SCL clock frequency

100

400

kHz

tBUF

bus free time between a STOP and START

condition

4.7

1.3

µs

tHD;STA

hold time (repeated) START condition

4.0

0.6

µs

tSU;STA

set-up time for a repeated START condition

4.7

0.6

µs

tSU;STO

set-up time for STOP condition

4.0

0.6

µs

tHD;DAT

data hold time

0-0-

tVD;ACK

data valid acknowledge time

0.6

µs

tVD;DAT

data valid time

LOW-level

0.6

µs

HIGH-level

0.6

µs

tSU;DAT

data set-up time

250

100

tLOW

LOW period of the SCL clock

4.7

1.3

µs

tHIGH

HIGH period of the SCL clock

4.0

0.6

µs

fall time of both SDA and SCL signals

0.3

µs

rise time of both SDA and SCL signals

0.3

µs

tSP

pulse width of spikes that must be

suppressed by the input ﬁlter

-50-50

Fig 17. I2C-bus timing

SDA

SCL

002aab271

tHD;STA

tLOW

tSU;DAT

tHD;DAT

tHIGH tSU;STA

tHD;STA

tSP

tSU;STO

tBUF

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