SC18IM700_2

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 02 — 10 August 2007

12 of 22

NXP Semiconductors

SC18IM700

9.2.2.4

Open-drain output configuration

The open-drain output configuration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port configured in this manner must have an external pull-up, typically a resistor

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

9.2.3 Programmable I/O pins state register (IOState)

When read, this register returns the actual state of all I/O pins. When written, each

register bit will be transferred to the corresponding I/O pin programmed as output.

be programmed with a ‘0’.

I2CAdr is not needed for device operation, but should be configured so that its address

This register determines the serial clock frequency. The various serial rates are shown in

Table 7. The frequency can be determined using the following formula:

I2CClkH determines the SCL HIGH period, and I2CClkL determines the SCL LOW period.

Fig 16. Open-drain output configuration

002aab883

pin latch data

GPIO pin

glitch rejection

input data

Table 6.

IOState - Programmable I/O pins state register (address 0x04h) bit description

Bit

Symbol

Description

7:0

IOLevel

Set the logic level on the output pins.

Write to this register:

logic 0 = set output pin to zero

logic 1 = set output pin to one

Read this register returns states of all pins.

bit frequency

7.3728

10

6

×

2

I 2CClkH

I 2CClkL

+

()

×

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