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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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P89LPC9321 датащи(PDF) 56 Page - NXP Semiconductors |
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P89LPC9321 датащи(HTML) 56 Page - NXP Semiconductors |
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56 / 70 page  P89LPC9321_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 9 December 2008 56 of 70 NXP Semiconductors P89LPC9321 8-bit microcontroller with accelerated two-clock 80C51 core Table 12. Dynamic characteristics (18 MHz) VDD = 3.0 V to 3.6 V unless otherwise specified. Tamb = −40 °C to +85 °C for industrial applications, unless otherwise specified.[1][2] Symbol Parameter Conditions Variable clock fosc =18MHz Unit Min Max Min Max fosc(RC) internal RC oscillator frequency nominal f = 7.3728 MHz trimmed to ± 1 % at Tamb =25 °C; clock doubler option = OFF (default) 7.189 7.557 7.189 7.557 MHz nominal f = 14.7456 MHz; clock doubler option = ON 14.378 15.114 14.378 15.114 MHz fosc(WD) internal watchdog oscillator frequency Tamb =25 °C 380 420 380 420 kHz fosc oscillator frequency 0 18 - - MHz Tcy(clk) clock cycle time see Figure 22 55 - - - ns fCLKLP low-power select clock frequency 0 8 - - MHz Glitch filter tgr glitch rejection time P1.5/RST pin - 50 - 50 ns any pin except P1.5/RST - 15 - 15 ns tsa signal acceptance time P1.5/RST pin 125 - 125 - ns any pin except P1.5/RST 50 - 50 - ns External clock tCHCX clock HIGH time see Figure 22 22 Tcy(clk) − tCLCX 22 - ns tCLCX clock LOW time see Figure 22 22 Tcy(clk) − tCHCX 22 - ns tCLCH clock rise time see Figure 22 -5 - 5 ns tCHCL clock fall time see Figure 22 -5 - 5 ns Shift register (UART mode 0) TXLXL serial port clock cycle time see Figure 21 16Tcy(clk) - 888 - ns tQVXH output data set-up to clock rising edge time see Figure 21 13Tcy(clk) - 722 - ns tXHQX output data hold after clock rising edge time see Figure 21 -Tcy(clk) + 20 - 75 ns tXHDX input data hold after clock rising edge time see Figure 21 -0 - 0 ns tXHDV input data valid to clock rising edge time see Figure 21 150 - 150 - ns SPI interface fSPI SPI operating frequency slave 0 CCLK ⁄ 6 0 3.0 MHz master - CCLK ⁄ 4 - 4.5 MHz TSPICYC SPI cycle time see Figure 23, 24, 25, 26 slave 6 ⁄ CCLK - 333 - ns master 4 ⁄ CCLK - 222 - ns |
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