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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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10F222 датащи(PDF) 12 Page - Microchip Technology |
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10F222 датащи(HTML) 12 Page - Microchip Technology |
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12 / 86 page  PIC10F220/222 DS41270E-page 10 © 2007 Microchip Technology Inc. FIGURE 3-1: BLOCK DIAGRAM TABLE 3-1: PINOUT DESCRIPTION Name Function Input Type Output Type Description GP0/AN0/ICSPDAT GP0 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN0 AN — Analog Input ICSPDAT ST CMOS In-Circuit programming data GP1/AN1/ICSPCLK GP1 TTL CMOS Bidirectional I/O pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. AN1 AN — Analog Input ICSPCLK ST — In-Circuit programming clock GP2/T0CKI/FOSC4 GP2 TTL CMOS Bidirectional I/O pin T0CKI ST — Clock input to TMR0 FOSC4 — CMOS Oscillator/4 output GP3/MCLR/VPP GP3 TTL — Input pin. Can be software programmed for internal weak pull-up and wake-up from Sleep on pin change. MCLR ST — Master Clear (Reset). When configured as MCLR, this pin is an active-low Reset to the device. Voltage on MCLR/VPP must not exceed VDD during normal device operation or the device will enter Programming mode. VPP HV — Programming voltage input VDD VDD P — Positive supply for logic and I/O pins VSS VSS P — Ground reference for logic and I/O pins Legend: I = Input, O = Output, I/O = Input/Output, P = Power, — = Not used, TTL = TTL input, ST = Schmitt Trigger input, AN = Analog Input Flash Program Memory 9-10 Data Bus 8 12 Program Bus Instruction Reg Program Counter RAM File Registers Direct Addr 5 RAM Addr 9 Addr MUX Indirect Addr FSR Reg STATUS Reg MUX ALU W Reg Device Reset Power-on Reset Watchdog Timer Instruction Decode & Control Timing Generation MCLR VDD, VSS Timer0 GPIO 8 8 GP3/MCLR/VPP GP2/T0CKI/FOSC4 GP1/AN1/ICSPCLK GP0/AN0/ICSPDAT 5-7 3 STACK1 STACK2 23 or 16 Internal RC Clock 512 x 12 or bytes Timer 256 x 12 ADC AN1 AN0 Absolute Voltage Reference |
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