10F222 datasheet(31/86 Pages) MICROCHIP

31 / 86 page

DS41270E-page 29

PIC10F220/222

7.0

ANALOG-TO-DIGITAL (A/D)

CONVERTER

The A/D converter allows conversion of an analog

signal into an 8-bit digital signal.

7.1

Clock Divisors

The A/D Converter has a single clock source setting,

INTOSC/4. The A/D Converter requires 13 TAD periods

to complete a conversion. The divisor values do not

affect the number of TAD periods required to perform a

conversion. The divisor values determine the length of

the TAD period.

7.2

Voltage Reference

Due to the nature of the design, there is no external

voltage reference allowed for the A/D Converter.

The A/D Converter reference voltage will always be

VDD.

7.3

Analog Mode Selection

The ANS<1:0> bits are used to configure pins for ana-

log input. Upon any Reset ANS<1:0> defaults to 11.

This configures pins AN0 and AN1 as analog inputs.

Pins configured as analog inputs are not available for

digital output. Users should not change the ANS bits

while a conversion is in process. ANS bits are active

regardless of the condition of ADON.

7.4

A/D Converter Channel Selection

The CHS bits are used to select the analog channel to

be sampled by the A/D Converter. The CHS bits

should not be changed during a conversion. To

acquire an analog signal, the CHS selection must

match one of the pin(s) selected by the ANS bits. The

Internal Absolute Voltage Reference can be selected

regardless of the condition of the ANS bits. All channel

selection information will be lost when the device

enters Sleep.

7.5

The GO/DONE bit

The GO/DONE bit is used to determine the status of a

conversion, to start a conversion and to manually halt a

conversion in process. Setting the GO/DONE bit starts

a conversion. When the conversion is complete, the A/

D Converter module clears the GO/DONE bit. A con-

version can be terminated by manually clearing the

GO/DONE bit while a conversion is in process. Manual

termination of a conversion may result in a partially

converted result in ADRES.

The GO/DONE bit is cleared when the device enters

Sleep, stopping the current conversion. The A/D Con-

verter does not have a dedicated oscillator, it runs off of

the system clock.

The GO/DONE bit cannot be set when ADON is clear.

7.6

Sleep

This A/D Converter does not have a dedicated A/D

Converter clock and therefore no conversion in Sleep

is possible. If a conversion is underway and a Sleep

command is executed, the GO/DONE and ADON bit

will be cleared. This will stop any conversion in process

and power-down the A/D Converter module to con-

serve power. Due to the nature of the conversion pro-

cess, the ADRES may contain a partial conversion. At

least 1 bit must have been converted prior to Sleep to

have partial conversion data in ADRES. The CHS bits

are reset to their default condition and CHS<1:0> = 11.

For accurate conversions, TAD must meet the following:

• 500 ns < TAD < 50

μs

•TAD = 1/(FOSC/divisor)

TABLE 7-1:

EFFECTS OF SLEEP AND WAKE ON ADCON0

Note:

Due to the fixed clock divisor, a conversion

will complete in 13 CPU instruction cycles.

Note:

The A/D Converter module consumes

power when the ADON bit is set even

when no channels are selected as analog

inputs. For low-power applications, it is

recommended that the ADON bit be

cleared when the A/D Converter is not in

use.

ANS1

ANS0

CHS1

CHS0

GO/DONE

ADON

Prior to Sleep

xxxx00

Prior to Sleep

xxxx11

Entering Sleep

Unchanged

1100

Wake

111100

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