10F222 datasheet(41/86 Pages) MICROCHIP

41 / 86 page

DS41270E-page 39

PIC10F220/222

FIGURE 8-6:

WATCHDOG TIMER BLOCK DIAGRAM

TABLE 8-4:

SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

8.7

Time-out Sequence, Power-down

and Wake-up from Sleep Status

Bits (TO/PD/GPWUF/CWUF)

The TO, PD and GPWUF bits in the STATUS register

can be tested to determine if a Reset condition has

been caused by a Power-up condition, a MCLR,

Watchdog Timer (WDT) Reset or wake-up on pin

change.

TABLE 8-5:

TO/PD/GPWUF STATUS AFTER RESET

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on

Power-On

Reset

Value on

All Other

Resets

N/A

OPTION

GPWU

GPPU

T0CS

T0SE

PSA

PS2

PS1

PS0

1111 1111

Legend: Shaded boxes = Not used by Watchdog Timer, – = unimplemented, read as ‘0’, u = unchanged.

(Figure 6-5)

Postscaler

Note 1:

T0CS, T0SE, PSA, PS<2:0> are bits in the OPTION register.

WDT Time-out

Watchdog

Timer

From Timer0 Clock Source

WDT Enable

Configuration

Bit

PSA

Postscaler

8-to-1 MUX

PS<2:0>

(Figure 6-4)

To Timer0

PSA

MUX

GPWUF

Reset Caused By

WDT wake-up from Sleep

WDT time-out (not from Sleep)

MCLR wake-up from Sleep

Power-up

MCLR not during Sleep

Wake-up from Sleep on pin change

Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’, q = value depends on condition.

Note 1:

The TO, PD and GPWUF bits maintain their status (u) until a Reset occurs. A low-pulse on the MCLR

input does not change the TO, PD or GPWUF Status bits.

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