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Revision 2.3

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AS3910

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.13.2 ANTICOLLISION

In this command, the bit oriented anticollision frame is used. There is no CRC, neither in the command send from PCD to PICC (part 1 of the bit

oriented anticollision frame), nor in the reply sent from PICC to PCD (part 2 of the bit oriented anticollision frame). Due to this configuration the bit

crc_rx of the Configuration Register 3 (address #03) has to be set to 1 before.

Sequence in case full bytes are transmitted (no collision during the transponder response):

1. Send the direct command Clear

2. Define the number of transmitted bytes for part1 of the bit oriented anticollision frame in the registers #0B and #0C. Bit 0 (antcl) of reg-

ister #0B has to be additionally set to 1 to indicate that anticollision frame is sent.

3. Write the bytes to be transmitted in the FIFO

4. Send the direct command Transmit without CRC

5. When all the data is transmitted an interrupt is sent to inform the microcontroller that transmission is finished (INTR due to end of trans-

mission)

6. When the reception of part2 of the bit oriented anticollision frame is finished and there was no collision detected, data is put in the FIFO

and an interrupt is sent to microcontroller (INTR due to end of receive), additionally the FIFO Status Register displays the number of

bytes in the FIFO, so the microcontroller can proceeded with downloading data from the FIFO.

Sequence in case of a split byte (no collision during transponder response):

1. Send the direct command Clear

2. Define the number of full bytes and the number of bits in the split byte to be transmitted in the registers #0B and #0C (bits ntx define the

number of full bytes, bits nbtx in register #0B define the number of bits in the split byte). Bit 0 (antcl) of register #0B has to be addition-

ally set to 1 to indicate that anticollision frame is sent.

3. Write the bytes to be transmitted in FIFO. Since the SPI communication is byte oriented 8 bits have to transferred also for split byte

(sent last), the MSB bits of split byte which are not transmitted are don’t care.

4. Send the direct command Transmit Without CRC

5. When all the data is transmitted an interrupt is sent to inform the microcontroller that the transmission is finished (INTR due to end of

transmission)

6. When the reception of part2 of the bit oriented anticollision frame is finished and there was no collision detected, data is put in the FIFO

and an interrupt is sent to the microcontroller (INTR due to end of receive), additionally the FIFO Status Register displays the number

of bytes in the FIFO so the microcontroller can proceeded with downloading data from the FIFO. First downloaded byte contains sec-

ond part of the split byte, so only the MSB part of byte which was not sent during transmit is valid.

8.13.3 Collision Detection

The AS3910 Framing block is able to detect the bit collision in case of presence of more ISO-14443A transponders. This feature is very useful

during the select sequence. The collision is detected during the ANTICOLLISION command (different transponders have different UIDs); it may

already be detected in the ATQA (answer to REQA or WUPA). When the bit collision is detected an interrupt is sent (INTR due to collision) and

the bit at which collision occurred is indicated in the Collision Register (#0A). In case of anticollision frame (indicated to the AS3910 by bit 0 of

register #0B) the bit collision position displayed in Collision Register is counted from beginning of anticollision frame (including the part which is

transmitted).

Please note that after getting the interrupt due to collision, the reader has to wait that the transponders finish sending their messages before

sending a new command. The end of transponder message is indicated by the End of Receive interrupt. It may also happen that the interrupt

due to collision and due to end of receive are read at the same time (in case reaction to the first interrupt is slow and collision happens at the end

of transponder message).

There is also a slight possibility that the end of message flag is just written to the Interrupt Register while it is being erased at the end of the

Interrupt Register read due to the collision interrupt. In such a case there is no end of receive interrupt. In case it is not clear whether the receive

logic is still processing response the Active Receive bit (rx_act) in FIFO Status Register can be consulted (See ISO-14443B, Reduction of TR0

and TR1 and Suppression of EOF/SOF in PICC Response on page 44 for details about Active Receive bit).

8.13.4 SELECT

The SELECT command uses standard frame, response to the SELECT command (SAK) contains also a CRC, so before sending this command

the configuration bit crc_rx of Configuration Register 3 has to be reset back to 0. Since the SELECT command contains CRC the direct

command Transmit with CRC can be used.