AS3910 datasheet(25/47 Pages) AMSCO

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www.austriamicrosystems.com/HF_RFID_Reader/AS3910

Revision 2.3

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AS3910

Data Sheet - A p p l i c a t i o n I n f o r m a t i o n

8.11.2 Configuration Registers

Note:

Default setting is set at power up and after Set Default command.

Note:

Default setting is set at power up and after Set Default command.

Table 12. Configuration Register 2

Address # 02: Configuration Register 2

type: RW

Bit

Name

Def.

Function

Comments

7sing

→ only RFO1 driver will be used

Choose between single and differential driving of

antenna.

envi

→ input applied to RFI1 is envelope

RF envelope input

tf2

→ reduces the gain for 11 dB in first stage

after peak detector

When both bits are set there is 17 dB gain

reduction in first stage

tf1

→ reduces the gain for 6 dB in first stage after

peak detector

3osc

→ 13.56MHz Xtal, 1 → 27.12MHz Xtal

Selector for crystal oscillator

out_cl1

out_cl0

out_cl

Selection of clock frequency on MCU_CLK

output. In case of “11”, MCU_CLK output is

permanently low.

out_cl0

3.39MHz

6.78 MHZ

13.56 MHZ

no output

Not used

Table 13. Configuration Register 3

Address # 03: Configuration Register 3 (ISO-14443A and NFC)

type: RW

Bit

Name

Def.

Function

Comments

7crc_rx

→ receive without CRC

For ISO-14443A anticollision.

no_par

→ no byte parity checking

When set to 1 parity bits are still detected

and removed before received data is put

in FIFO, but there is no check for their

correctness

5p_len3

p_len3

p_len2

p_len1

p_len0

reduction

Modulation pulse reduction,

Defined in number of 13.56 MHz clock

periods

p_len2

000

p_len1

74ns

2p_len0

1106ns

Not used

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