www.austriamicrosystems.com/HF_RFID_Reader/AS3910

Revision 2.3

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AS3910

Data Sheet - D e t a i l e d D e s c r i p t i o n

7.0.1 Transmitter

The Transmitter incorporates drivers, which drive external antenna through pads RFO1 and RFO2. Single sided and differential driving is

possible. The transmitter block additionally contains a subblock, which modulates transmitted signal for communication reader to transponder

(OOK or configurable AM modulation).

The AS3910 transmitter is indented to directly drive antennas (without 50

Ω cable, usually antenna is on the same PCB). Operation with 50Ω

cable is also possible, but in that case some of the advanced features are not possible.

7.0.2 Receiver

The receiver detects transponder modulation superimposed on the 13.56MHz carrier signal. The receiver chain is composed of a peak detector

followed by two stages with gain and filtering function and a final digitizer stage. The filter characteristics are adjusted to optimize performance

over different ISO modes and data rates (subcarrier frequencies from 212 kHz to 848 kHz are supported). The receiver chain input is the RFI1

pin; output of digitizer stage is demodulated subcarrier signal. Receiver also contains a subblock, which helps to detect the presence of external

RF field in NFCIP target mode. The receiver chain incorporates several features, which enable reliable operation in challenging phase and noise

conditions.

7.0.3 Phase and Amplitude Detector

The phase detector observes the phase difference between the transmitter output signals (RFO1 and RFO2) and the pad signals RFI1 and RFI2.

The pad signals RFI1 and RFI2 are proportional to the signal on the antenna LC tank. RFI1 and RFI2 signals are also used to run the self-mixer,

which generates output proportional to their amplitude. The phase detector and self mixer blocks are used for several purposes:

Variation of RFI1 and RFI2 phase is used to perform PM demodulation

Average phase difference between RFOx pins and RFIx pins is used to check antenna tuning

Output of mixer is used to measure amplitude of signal present on pins RFI1 and RFI2

7.0.4 A/D Converter

The AS3910 contains a built-in A/D Converter. Its input can be multiplexed from different sources and is used in several applications

(measurement of RF amplitude, calibration of modulation depth, checking of the antenna LC tank resonance, A/D conversion of signal applied to

pin AD_IN). The result of A/D conversion is stored in a register, which can be read through the SPI interface.

7.0.5 External Field Detector

The external field detector is a low power block, which is switched on in NFCIP target mode to detect the presence of initiator field. It is also used

during the NFCIP Collision Avoidance procedure.

7.0.6 Quartz Crystal Oscillator

The quartz crystal oscillator can operate with 13.56MHz and 27.12MHz crystals. At start-up the transconductance of the oscillator is increased to

achieve fast start-up. Since the start-up time varies depending on crystal type, temperature and other parameters, the oscillator amplitude is

observed and an interrupt is sent when stable operation is reached to inform the controller that the clock signal is stable and reader field can be

switched on.

It also provides a clock signal to the external microcontroller (MCU_CLK) according to setting in the control register.

7.0.7 Power Supply Regulators

Integrated power supply regulators ensure high power supply rejection of a complete reader system. At power up, the regulators are transparent.

In case PSRR of the reader system has to be improved, then the command Adjust Regulators is sent. As a result of this command, the power

supply level of VDD is measured in maximum load conditions and the regulated voltage reference is set 250mV below this measured level to

assure a stable regulated supply. The resulting regulated voltage is stored in a register. It is also possible to define regulated voltage by writing a

configuration register. In order to decouple any noise sources from different parts of IC there are two regulators integrated with separated

external blocking capacitors (regulated voltage of both is the same). One regulator is for the analog blocks, the other one is for the antenna

drivers. Logic and digital I/O pads are supplied directly from VDD (negative supply pin for logic and digital I/O is separated to avoid coupling of

logic induced noise in the substrate). This block additionally generates a reference voltage for the analog processing (AGD - analog ground).

This voltage also has an associated external buffer capacitor.

7.0.8 POR and Bias

This block contains the bias current and voltage generator, which provides bias currents and reference voltages to all other blocks. It also

incorporates a Power on Reset (POR) circuit, which provides a reset at power-up and at low supply levels.