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ST7713 датащи(PDF) 24 Page - Sitronix Technology Co., Ltd. |
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ST7713 датащи(HTML) 24 Page - Sitronix Technology Co., Ltd. |
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24 / 159 page ![]() ST7713 Ver 1.6 2008-05 24 8.3 Serial interface characteristics (3-line serial) Fig. 8.3.1 3-line serial interface timing Signal Symbol Parameter Min Max Unit Description TCSS Chip select setup time 45 ns TCSH Chip select hold time 45 ns TCSS Chip select setup time 12 ns TSCC Chip select hold time 20 ns CSX TCHW Chip select “H” pulse width 0 ns TSCYCW Serial clock cycle (Write) 66 ns TSHW SCL “H” pulse width (Write) 15 ns TSLW SCL “L” pulse width (Write) 15 ns TSCYCR Serial clock cycle (Read) 150 ns TSHR SCL “H” pulse width (Read) 60 ns SCL TSLR SCL “L” pulse width (Read) 60 ns TSDS Data setup time 10 ns TSDH Data hold time 10 ns TACC Access time 10 40 ns SDA (DIN) (DOUT) TOH Output disable time 40 ns For maximum CL=30pF For minimum CL=8pF Table 8.3: 3-line Serial Interface Characteristics Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. |
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