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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7713 датащи(PDF) 86 Page - Sitronix Technology Co., Ltd. |
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ST7713 датащи(HTML) 86 Page - Sitronix Technology Co., Ltd. |
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86 / 159 page  ST7713 Ver 1.6 2008-05 86 9.18.3 Reset Timing Table 9.18.3.1 Reset input timing VSS=0V, VDDI=1.65V to 1.95V, VDD=2.6V to 2.9V, Ta = -30 to 70 ) ℃ Symbol Parameter Related Pins MIN TYP MAX Note Unit tRESW (*1) Reset low pulse width RESX 10 - - - us tREST (*2) Reset complete time - 120 - - - ms Note 1. Spike due to an electrostatic discharge on RESX line does not cause irregular system reset according to the table below. Note 2. It will be necessary to wait 120msec before sending next command; this is allowing time for the supply voltages and clock circuits to stabilize. Note 3. During Reset Complete Time, ID2 and VCOMOF value in OTP will be latched to internal register during this period. This loading is done every time when there is H/W reset complete time (tREST) within 120ms after a rising edge of RESX. Note 4. Spike Rejection also applies during a valid reset pulse as shown below: |
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