ST7713 datasheet(53/159 Pages) SITRONIX

53 / 159 page

ST7713

Ver 1.6

2008-05

9.9 RGB interface

9.9.1 General Description

The module uses 6, 16 and 18-bit parallel RGB interface which includes: VS, HS, DE, PCLK, D[17:0]. The interface is

activated after Power-On sequence (See section Power-On/Off Sequence)

Pixel clock (PCLK) is running all the time without stopping and it is used to enter VS, HS, DE and D[17:0] states at the rising

edge of the PCLK. The PCLK cannot be used as continues internal clock for other functions of the display module e.g.

Sleep-In mode etc.

Vertical synchronization (VS) is used to tell the driver when a new frame of the display is beginning. This is negative (‘0’,

low) active and its state is read by the driver at the rising edge of he PCLK signal.

Horizontal synchronization (HS) is used to tell the driver when a new line of the frame is beginning. This is negative (‘0’, low)

active and its state is read by the driver at the rising edge of the PCLK signal.

Data Enable (DE) is used to tell the driver when the RGB information will be transferred ti the driver. This is a positive (‘1’,

high) active and its state is read by the driver at the rising edge of the PCLK signal.

D[17:0] (18-bit: R5-R0, G5-G0 and B5-B0; 16-bit: R4-R0, G5-G0 and B4-B0) are used to tell what is the information of the

image that is transferred on the display (When DE=’1’ and at the rising edge of PCLK). D[17:0] can be ‘0’ (low) or ‘1’ (high).

These lines are read by the driver at the rising edge of the PCLK signal.

The PCLK cycle is described in the following figure.

Fig. 9.9.1 PCLK cycle

Note: PCLK is an unsynchronized signal (It can be stopped).

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