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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7713 датащи(PDF) 23 Page - Sitronix Technology Co., Ltd. |
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ST7713 датащи(HTML) 23 Page - Sitronix Technology Co., Ltd. |
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23 / 159 page  ST7713 Ver 1.6 2008-05 23 8.2 Parallel interface characteristics: 18, 16, 9 or 8-bits bus (6800-series MCU interface) CSX D/CX D[17:0] write D[17:0] read VIH VIL VIH VIL TCHW TCHW TCSH TCSF TAST TRCS/TRCSFM /WX E RX E TCS VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL TAHT TWC TWRH TWRL TDST TDHT TRDH/TRDHFM TRDL/TRDLFM TRC/TRCFM TRAT/TRATFM TODH Fig. 8.2.1 Parallel interface timing characteristics (6800-series MCU interface) Signal Symbol Parameter Min Max Unit Description TAST Address setup time 5 ns D/CX TAHT Address hold time (Write/Read) 10 ns - TCHW Chip select “H” pulse width 0 ns TCS Chip select setup time (Write) 20 ns TRCS Chip select setup time (Read ID) 20 ns TRCSFM Chip select setup time (Read FM) 20 ns TCSF Chip select wait time (Write/Read) 5 ns CSX TCSH Chip select hold time 20 ns - TWC Write cycle 66 ns TWRH Control pulse “H” duration 25 ns WRX TWRL Control pulse “L” duration 15 ns TRC Read cycle (ID) 160 ns TRDH Control pulse “H” duration (ID) 90 ns RDX (ID) TRDL Control pulse “L” duration (ID) 45 ns When read ID data TRCFM Read cycle (FM) 160 ns TRDHFM Control pulse “H” duration (FM) 90 ns RDX (FM) TRDLFM Control pulse “L” duration (FM) 45 ns When read from frame memory TDST Data setup time 15 ns TDHT Data hold time 15 ns TRAT Read access time (ID) 40 ns TRATFM Read access time (FM) 340 ns D[17:0] TODH Output disable time 20 80 ns For maximum CL=30pF For minimum CL=8pF Note 1: VDDI=1.6 to 3.3V, VDD=2.5 to 3.3V, AGND=DGND=0V, Ta=-30 to 70℃ Note 2: The rising time and falling time (Tr, Tf) of input signal are specified at 15 ns or less. Logic high and low levels are specified as 30% and 70% of VDDI for Input signals. |
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