HT68F20 datasheet(44/210 Pages) HOLTEK

44 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev. 1.00

November 3, 2009

Watchdog Timer

The Watchdog Timer is provided to prevent program

malfunctions or sequences from jumping to unknown lo-

cations, due to certain uncontrollable external events

such as electrical noise.

Watchdog Timer Clock Source

The Watchdog Timer clock source is provided by the in-

ternal clock, fS, which is in turn supplied by one of two

sources selected by configuration option: fSUB or fSYS/4.

The fSUB clock can be sourced from either the LXT or

LIRC oscillators, again chosen via a configuration op-

tion. The Watchdog Timer source clock is then subdi-

vided by a ratio of 2

8 to 215 to give longer timeouts, the

actual value being chosen using the WS2~WS0 bits in

the WDTC register. The LIRC internal oscillator has an

approximate period of 32kHz at a supply voltage of 5V.

However, it should be noted that this specified internal

clock period can vary with VDD, temperature and pro-

cess variations. The LXT oscillator is supplied by an ex-

ternal 32.768kHz crystal. The other Watchdog Timer

clock source option is the fSYS/4 clock. The Watchdog

Timer clock source can originate from its own internal

LIRC oscillator, the LXT oscillator or fSYS/4. It is divided

by a value of 2

8 to 215, using the WS2~WS0 bits in the

WDTC register to obtain the required Watchdog Timer

time-out period.

Watchdog Timer Control Register

A single register, WDTC, controls the required timeout

period as well as the enable/disable operation. This reg-

ister together with several configuration options control

the overall operation of the Watchdog Timer.

· WDTC Register

Bit

76543210

Name

FSYSON

WS2

WS1

WS0

WDTEN3

WDTEN2

WDTEN1

WDTEN0

R/W

POR

01111010

Bit 7

FSYSON: fSYS Control in IDLE Mode

0: Disable

1: Enable

Bit6~4

WS2, WS1, WS0 : WDT time-out period selection

000: 256/fS

001: 512/fS

010: 1024/fS

011: 2048/fS

100: 4096/fS

101: 8192/fS

110: 16384/fS

111: 32768/fS

These three bits determine the division ratio of the Watchdog Timer source clock, which in turn

determines the timeout period.

Bit3~0

WDTEN3, WDTEN2, WDTEN1, WDTEN0 : WDT Software Control

1010: Disable

Other: Enable

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