HT68F20 datasheet(89/210 Pages) HOLTEK

89 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev.1.00

November 3, 2009

Timer/Counter Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

Timer/Counter Mode operates in an identical way to the

Compare Match Output Mode generating the same in-

terrupt flags. The exception is that in the Timer/Counter

Mode the TM output pin is not used. Therefore the

above description and Timing Diagrams for the Com-

pare Match Output Mode can be used to understand its

function. As the TM output pin is not used in this mode,

the pin can be used as a normal I/O pin or other

pin-shared function.

PWM Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

tion within the TM is useful for applications which require

functions such as motor control, heating control, illumi-

nation control etc. By providing a signal of fixed fre-

quency but of varying duty cycle on the TM output pin, a

square wave AC waveform can be generated with vary-

ing equivalent DC RMS values.

As both the period and duty cycle of the PWM waveform

can be controlled, the choice of generated waveform is

extremely flexible. In the PWM mode, the TnCCLR bit

has no effect on the PWM operation. Both of the CCRA

and CCRP registers are used to generate the PWM

waveform, one register is used to clear the internal

counter and thus control the PWM waveform frequency,

while the other one is used to control the duty cycle.

Which register is used to control either frequency or duty

cycle is determined using the TnDPX bit in the TMnC1

can therefore be controlled by the values in the CCRA

and CCRP registers.

An interrupt flag, one for each of the CCRA and CCRP,

will be generated when a compare match occurs from

either Comparator A or Comparator P. The TnOC bit in

the TMnC1 register is used to select the required polar-

ity of the PWM waveform while the two TnIO1 and

TnIO0 bits are used to enable the PWM output or to

force the TM output pin to a fixed high or low level. The

TnPOL bit is used to reverse the polarity of the PWM

output waveform.

CCRP

CCRA

Counter

Value

Counter Cleared

by CCRP

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

PWM Output

TM Pin

TnOC = 1

TnON bit

PWM Duty Cycle

set by CCRA

PWM Period

set by CCRP

TnIO1, TnI O0 = 10 PWM Out put

TnIO 1, TnIO0 = 00

Output Inactive

TnIO1, TnIO 0 = 10

Interrupts

still generat ed

Here TnIO1, TnI O0 = 00

Out put Forced to Inactive

level but PWM function

keeps running internally

TnIIO1, TnIO0 = 10

Resume PWM O utput

Counter Stop

if TnO N bit low

Count er reset

when TnON

ret urns high

PWM resumes operat ion

Output remains at same level

Time

TnPOL bit

O utput Inverts

When TnPOL = 1

TM Pin

TnOC = 0

TnPAU bit

Resume

Pause

DPX = 0; TnM1, TnM0 = 10

PWM Mode - TnDPX = 0

Note:

1. Here TnDPX=0- Counter cleared by CCRP

2. Counter Clear sets PWM Period

3. Internal PWM function continues even when TnIO1, TnIO0 = 00 or 01

4. TnCCLR bit has no influence on PWM operation

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