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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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HT68F20 датащи(PDF) 63 Page - Holtek Semiconductor Inc |
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HT68F20 датащи(HTML) 63 Page - Holtek Semiconductor Inc |
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63 / 210 page  HT68F20/HT68F30/HT68F40/HT68F50/HT68F60 Rev. 1.00 63 November 3, 2009 · PGPU Register ¨ HT68F60 Bit 76543210 Name ¾¾¾¾¾¾ D1 D0 R/W ¾¾¾¾¾¾ R/W R/W POR ¾¾¾¾¾¾ 00 Bit 7~2 ²¾² Unimplemented, read as ²0² Bit 1~0 PGPU: Port G bit 1 ~ bit 0 Pull-High Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. · PAWU Register Bit 76543210 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 00000000 Bit 7~0 PAWU: Port A bit 7 ~ bit 0 Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PGC, to control the input/output configuration. With this con- trol register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corre- sponding bit of the control register must be written as a ²1². This will then allow the logic state of the input pin to be di- rectly read by instructions. When the corresponding bit of the control register is written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. · PAC Register Bit 76543210 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 11111111 · PBC Register ¨ HT68F40/HT68F50/HT68F60 Bit 76543210 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 11111111 |
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