HT68F20 datasheet(87/210 Pages) HOLTEK

87 / 210 page

HT68F20/HT68F30/HT68F40/HT68F50/HT68F60

Rev.1.00

November 3, 2009

Compact Type TM Operating Modes

The Compact Type TM can operate in one of three oper-

ating modes, Compare Match Output Mode, PWM

Mode or Timer/Counter Mode. The operating mode is

selected using the TnM1 and TnM0 bits in the TMnC1

Compare Match Output Mode

To select this mode, bits TnM1 and TnM0 in the TMnC1

²00² respectively. In this mode

once the counter is enabled and running it can be

cleared by three methods. These are a counter over-

flow, a compare match from Comparator A and a com-

pare match from Comparator P. When the TnCCLR bit is

low, there are two ways in which the counter can be

cleared. One is when a compare match occurs from

Comparator P, the other is when the CCRP bits are all

zero which allows the counter to overflow. Here both

TnAF and TnPF interrupt request flags for the Compara-

tor A and Comparator P respectively, will both be gener-

ated.

If the TnCCLR bit in the TMnC1 register is high then the

counter will be cleared when a compare match occurs

from Comparator A. However, here only the TnAF inter-

rupt request flag will be generated even if the value of

the CCRP bits is less than that of the CCRA registers.

Therefore when TnCCLR is high no TnPF interrupt re-

quest flag will be generated. If the CCRA bits are all

zero, the counter will overflow when its reaches its maxi-

mum 10-bit, 3FF Hex, value, however here the TnAF in-

terrupt request flag will not be generated.

As the name of the mode suggests, after a comparison

is made, the TM output pin will change state. The TM

output pin condition however only changes state when

an TnAF interrupt request flag is generated after a com-

pare match occurs from Comparator A. The TnPF inter-

rupt request flag, generated from a compare match

occurs from Comparator P, will have no effect on the TM

output pin. The way in which the TM output pin changes

state are determined by the condition of the TnIO1 and

TnIO0 bits in the TMnC1 register. The TM output pin can

be selected using the TnIO1 and TnIO0 bits to go high,

to go low or to toggle from its present condition when a

compare match occurs from Comparator A. The initial

condition of the TM output pin, which is setup after the

TnON bit changes from low to high, is setup using the

TnOC bit. Note that if the TnIO1 and TnIO0 bits are zero

then no pin change will take place.

CCRA

CCRP

0x3FF

Counter

Value

Counter

overflow

CCRA Int.

Flag TnAF

CCRP Int.

Flag TnPF

CCRP > 0

Counter cleared by CCRP value

TM O/P Pin

TnON bit

Pause

Count er

Reset

Output Pin

Reset to initial value

Output Pin set

to Initial Level

Lowif TnOC= 0

Output Toggle

with TnAF flag

Here TnIO 1, TnIO0 = 11

Toggle Output Select

Now TnIO1, TnIO0 = 10

Act ive High Output

Select

Output not af fect ed by TnAF flag

Remains High until reset by TnON bit

TnCCRL = 0; TnM1, TnM0 = 00

TnPAU bit

Resume

Stop

Time

CCRP > 0

CCRP = 0

TnPOL bit

Output inverts

when TnPO L is high

Compare Match Output Mode - TnCCLR = 0

Note:

1. With TnCCLR = 0 the Comparator P match will clear the counter

2. TM output pin controlled only by TnAF flag

3. Output pin reset to initial state by TnON bit rising edge

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