ATmega16HVB datasheet(58/273 Pages) ATMEL

58 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

13. External Interrupts

13.1

Overview

The External Interrupts are triggered by the INT3:0 pin or any of the PCINT11:0 pins. Observe

that, if enabled, the interrupts will trigger even if the INT3:0 or PCINT11:0 pins are configured as

outputs. This feature provides a way of generating a software interrupt.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up

as indicated in the specification for the ”EICRA – External Interrupt Control Register A” on page

58. When the external interrupt is enabled and is configured as level triggered, the interrupt will

trigger as long as the pin is held low. Interrupts are detected asynchronously. This implies that

these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The I/O clock is halted in all sleep modes except Idle mode.

The Pin change interrupt PCI1 will trigger if any enabled PCINT11:4 pin toggles and Pin change

interrupts PCI0 will trigger if any enabled PCINT3:0 pin toggles. PCMSK1 and PCMSK0 Regis-

ters control which pins contribute to the pin change interrupts. Pin change interrupts on

PCINT11:0 are detected asynchronously. This implies that these interrupts can be used for wak-

ing the part also from sleep modes other than Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-save, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT fuses as described in ”Clock

Systems and their Distribution” on page 25.

13.2

13.2.1

EICRA – External Interrupt Control Register A

• Bits 7:0 – ISCn: External Interrupt Sense Control Bits

The External Interrupts 3:0 are activated by the external pins INT3:0 if the SREG I-flag and the

corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that

activate the interrupts are defined in Table 13-1 on page 59. Edges on INT3..INT0 are registered

asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 32-

11 on page 233 will generate an interrupt. Shorter pulses are not guaranteed to generate an

interrupt. If low level interrupt is selected, the low level must be held until the completion of the

currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will

generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an

interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its Interrupt

Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt

flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Regis-

ter before the interrupt is re-enabled.

Bit

765

432

(0x69)

ISC31

ISC30

ISC21

ISC20

ISC11

ISC10

ISC01

ISC00

EICRA

Read/Write

R/W

Initial Value

ATmega16HVB датащи(PDF) 58 Page - ATMEL Corporation

ATmega16HVB датащи(HTML) 58 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL