ATmega16HVB datasheet(50/273 Pages) ATMEL

50 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is

enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt

Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in

the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE

and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use-

ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and

System Reset Mode, WDIE must be set after each interrupt. This should however not be done

within the interrupt service routine itself, as this might compromise the safety-function of the

Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a Sys-

tem Reset will be applied.

Note:

1. WDTON Fuse set to “0” means programmed, “1” means unprogrammed.

• Bit 5, 2:0 - WDP3:0 : Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 11-2.

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,

and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is

set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during con-

ditions causing failure, and a safe start-up after the failure.

• Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 11-2 on page 51.

Table 11-1.

Watchdog Timer Configuration

WDTON(1)

WDE

WDIE

Mode

Action on Time-out

Stopped

None

Interrupt Mode

Interrupt

System Reset Mode

Reset

Interrupt and System Reset

Mode

Interrupt, then go to System Reset

Mode

System Reset Mode

Reset

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