ATmega16HVB datasheet(87/273 Pages) ATMEL

87 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

but in 16-bit Input Capture mode the Output Compare Unit cannot be used as there are no free

Output Compare Register(s). Even though the Input Capture register is called ICRn in this sec-

tion, it is referring to the Output Compare Register(s). For more information on how to access

the 16-bit registers refer to ”Accessing Registers in 16-bit Mode” on page 90.

When a change of the logic level (an event) occurs on the Input Capture pin (ICPx), and this

change confirms to the setting of the edge detector, a capture will be triggered. When a capture

is triggered, the value of the counter (TCNTn) is written to the Input Capture Register (ICRn).

The Input Capture Flag (ICFn) is set at the same system clock as the TCNTn value is copied into

Input Capture Register. If enabled (TICIEn=1), the Input Capture Flag generates an Input Cap-

ture interrupt. The ICFn flag is automatically cleared when the interrupt is executed. Alternatively

the ICFn flag can be cleared by software by writing a logical one to its I/O bit location.

17.6.1

Input Capture Trigger Source

The default trigger source for the Input Capture unit is the I/O port PB0 in Timer/Counter0 and

the Battery Protection Interrupt in Timer/Counter1. Alternatively can the osi_posedge pin on the

Oscillator Sampling Interface in Timer/Counter0 and Voltage Regulator Interrupt in

Timer/Counter1 be used as trigger sources. The osi_posedge pin in Timer/Counter0 Control

bit. Be aware that changing trigger source can trigger a capture. The Input Capture Flag must

therefore be cleared after the change.

Both Input Capture inputs are sampled using the same technique. The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. An Input Capture on

Timer/Counter0 can also be triggered by software by controlling the port of the PB0 pin.

17.6.2

Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used by the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNCn) bit in

Timer/Counter Control Register n B (TCCRnB). When enabled the noise canceler introduces

additional four system clock cycles of delay from a change applied to the input, to the update of

the ICRn Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

17.6.3

Using the Input Capture Unit

The main challenge when using the Input Capture unit is to assign enough processor capacity

for handling the incoming events. The time between two events is critical. If the processor has

not read the captured value in the ICRn Register before the next event occurs, the ICRn will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICRn Register should be read as early in the inter-

rupt handler routine as possible. The maximum interrupt response time is dependent on the

maximum number of clock cycles it takes to handle any of the other interrupt requests.

Measurement of an external signal duty cycle requires that the trigger edge is changed after

each capture. Changing the edge sensing must be done as early as possible after the ICRn

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