ATmega16HVB datasheet(89/273 Pages) ATMEL

89 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

17.7.1

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNTnH/L Register will block any Compare Match that occur in

the next timer clock cycle, even when the timer is stopped. This feature allows OCRnA/B to be

initialized to the same value as TCNTn without triggering an interrupt when the Timer/Counter

clock is enabled.

17.7.2

Using the Output Compare Unit

Since writing TCNTnH/L will block all Compare Matches for one timer clock cycle, there are risks

involved when changing TCNTnH/L when using the Output Compare Unit, independently of

whether the Timer/Counter is running or not. If the value written to TCNTnH/L equals the

OCRnA/B value, the Compare Match will be missed.

17.8

Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk

Tn) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 17-6 on page 89 contains timing data for basic Timer/Counter operation.

The figure shows the count sequence close to the MAX value.

Figure 17-6. Timer/Counter Timing Diagram, no Prescaling

Figure 17-7 on page 89 shows the same timing data, but with the prescaler enabled.

Figure 17-7. Timer/Counter Timing Diagram, with Prescaler (f

clk_I/O/8)

Figure 17-8 on page 90 shows the setting of OCFnA and OCFnB in Normal mode.

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

TOVn

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

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