ATmega16HVB datasheet(94/273 Pages) ATMEL

94 / 273 page

8042A–AVR–07/09

ATmega16HVB/32HVB

17.10 Register Description

17.10.1

TCCRnA – Timer/Counter n Control Register A

• Bit 7– TCWn: Timer/Counter Width

When this bit is written to one 16-bit mode is selected. Timer/Counter n width is set to 16-bits

and the Output Compare Registers OCRnA and OCRnB are combined to form one 16-bit Output

Compare Register. Because the 16-bit registers TCNTnH/L and OCRnB/A are accessed by the

AVR CPU via the 8-bit data bus, special procedures must be followed. These procedures are

described in section ”Accessing Registers in 16-bit Mode” on page 90.

• Bit 6– ICENn: Input Capture Mode Enable

The Input Capture Mode is enabled when this bit is written to one.

• Bit 5 – ICNCn: Input Capture Noise Canceler

Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-

vated, the input from the Input Capture Source is filtered. The filter function requires four

successive equal valued samples of the Input Capture Source for changing its output. The Input

Capture is therefore delayed by four System Clock cycles when the noise canceler is enabled.

• Bit 4 – ICESn: Input Capture Edge Select

This bit selects which edge on the Input Capture Source that is used to trigger a capture event.

When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and when the

ICESn bit is written to one, a rising (positive) edge will trigger the capture. When a capture is trig-

gered according to the ICESn setting, the counter value is copied into the Input Capture

Input Capture Interrupt, if this interrupt is enabled.

• Bit 3 - ICSn: Input Capture Select

When written logic one, this bit enables the input capture function in Timer/Counter n to be trig-

gered by the alternative Input Capture Source. To make the comparator trigger the

Timer/Counter n Input Capture interrupt, the TICIEn bit in the Timer Interrupt Mask Register

(TIMSK) must be set. See Table 17-3 on page 88 and Table 17-4 on page 88.

• Bits 2:0 – Res: Reserved Bits

These bits are reserved bits in the ATmega16HVB/32HVB and will always read as zero.

• Bit 0 – WGMn0: Waveform Generation Mode

This bit controls the counting sequence of the counter, the source for maximum (TOP) counter

value, see Figure 17-6 on page 89. Modes of operation supported by the Timer/Counter unit are:

Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see ”Timer/Counter

Timing Diagrams” on page 89).

Bit

765

0x24 (0x44)

TCWn

ICENn

ICNCn

ICESn

ICSn

–

WGMn0

TCCRnA

Read/Write

R/W

Initial Value

ATmega16HVB датащи(PDF) 94 Page - ATMEL Corporation

ATmega16HVB датащи(HTML) 94 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL