AT89LP428 datasheet(100/149 Pages) ATMEL

100 / 149 page

100

3654A–MICRO–8/09

AT89LP428/828

18.1

Analog Input Muxes

The positive input terminal of each comparator may be connected to any of the four analog input

pins by changing the CSA

1-0 or CSB1-0 bits in ACSRA and ACSRB. When changing the analog

input pins, the comparator must be disconnected from its inputs by clearing the CONA or CONB

bits. The connection is restored by setting the bits again after the muxes have been modified.

CLR

; Disable comparator interrupts

ANL

ACSRA, #0DFh

; Clear CONA to disconnect COMP A

...

; Modify CSA or RFA bits

ORL

ACSRA, #020h

; Set CONA to connect COMP A

ANL

ACSRA, #0EFh

; Clear any spurious interrupt

SETB

; Re-enable comparator interrupts

The corresponding comparator interrupt should not be enabled while the inputs are being

changed, and the comparator interrupt flag must be cleared before the interrupt is re-enabled in

order to prevent an unintentional interrupt request.

18.2

Internal Reference Voltage

The negative input terminal of each comparator may be connected to an internal voltage refer-

ence by changing the RFB

1-0 or RFA1-0 bits in AREF. The internal reference voltage, VAREF, is

set to 1.25V ±5%. The voltage reference also provides two additional voltage levels approxi-

mately 125 mV above and below V

AREF. These levels may be used to configure the comparators

as an internally referenced window comparator with up to four input channels. Changing the ref-

erence input must follow the same routine used for changing the positive input as described in

the “Analog Input Muxes” section.

18.3

Comparator Interrupt Debouncing

The comparator output is normally sampled every clock cycle. The conditions on the analog

inputs may be such that the comparator output will toggle excessively. This is especially true if

applying slow moving analog inputs. Three debouncing modes are provided to filter out this

noise for edge-triggered interrupts. In debouncing mode, the comparator uses Timer 1 to modu-

late its sampling time when CxC

1-0 = 00B. When a relevant transition occurs, the comparator

waits until two Timer 1 overflows have occurred before resampling the output. If the new sample

agrees with the expected value, CFx is set. Otherwise, the event is ignored. The filter may be

tuned by adjusting the time-out period of Timer 1. Because Timer 1 is running free, the

debouncer must wait for two overflows to guarantee that the sampling delay is at least 1 time-out

period. Therefore, after the initial edge event, the interrupt may occur between 1 and 2 time-out

periods later. See Figure 18-2. When the comparator clock is provided by one of the timer over-

flows, i.e. CxC

1-0 = 00B, any change in the comparator output must be valid after 4 samples to

be accepted as an edge event.

Figure 18-2. Negative Edge with Debouncing Example

Comparator Out

Timer 1 Overflow

CFx

Start

Compare

(rejected)

Compare

(accepted)

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