AT89LP428 datasheet(78/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

interrupted by a data byte. An address byte, however, interrupts all slaves. Each slave can

examine the received byte and see if it is being addressed. The addressed slave clears its SM2

bit and prepares to receive the data bytes that follows. The slaves that are not addressed set

their SM2 bits and ignore the data bytes.

The SM2 bit can be used to check the validity of the stop bit in Mode 1. In a Mode 1 reception, if

SM2 = 1, the receive interrupt is not activated unless a valid stop bit is received.

Notes:1. SMOD0 is located at PCON.6.

2. f

osc = oscillator frequency. The baud rate depends on SMOD1 (PCON.7).

Table 16-1.

SCON – Serial Port Control Register

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE

SM1

SM2

REN

TB8

RB8

Bit

(SMOD0 = 0/1)(1)

Symbol

Function

Framing error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames and must be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. FE will be set

regardless of the state of SMOD0.

SM0

Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0)

SM1

Serial Port Mode Bit 1

SM2

Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received

9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 =

1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address.

In Mode 0, SM2 determines the idle state of the shift clock such that the clock is the inverse of SM2, i.e. when SM2 = 0

the clock idles high and when SM2 = 1 the clock idles low.

REN

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

TB8

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In Mode 0, setting TB8

enables Timer 1 as the shift clock generator.

RB8

In Modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In

Mode 0, RB8 is not used.

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the

other modes, in any serial reception (except see SM2). Must be cleared by software.

SM0

SM1

Mode

Description

Baud Rate

(2)

shift register

osc/2 or fosc/4 or Timer 1

8-bit UART

variable (Timer 1 or Timer 2)

9-bit UART

osc/32 or fosc/16

9-bit UART

variable (Timer 1 or Timer 2)

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