AT89LP428 datasheet(99/149 Pages) ATMEL

99 / 149 page

3654A–MICRO–8/09

AT89LP428/828

interrupt flag are not guaranteed to be stable for 10 µs. The corresponding comparator interrupt

should not be enabled during that time, and the comparator interrupt flag must be cleared before

the interrupt is enabled in order to prevent an immediate interrupt service. Before enabling the

comparators, the analog inputs should be tristated by putting P2.4, P2.5, P2.6 and P2.7 into

input-only mode. See “Port 2 Analog Functions” on page 38.

Figure 18-1. Dual Comparator Block Diagram

Each comparator may be configured to cause an interrupt under a variety of output value condi-

tions by setting the CMx

2-0 bits in ACSRx. The comparator interrupt flags CFx in ACSRx are set

whenever the comparator outputs match the conditions specified by CMx

2-0. The flags may be

polled by software or may be used to generate an interrupt and must be cleared by software.

Both comparators share a common interrupt vector. If both comparators are enabled, the user

needs to read the flags after entering the interrupt service routine to determine which compara-

tor caused the interrupt.

The CAC

1-0 and CBC1-0 bits in AREF control when the comparator interrupts sample the com-

parator outputs. Normally, the outputs are sampled every clock system; however, the outputs

may also be sampled whenever Timer 0, Timer 1 or Timer 2 overflows. These settings allow the

comparators to be sampled at a specific time or to reduce the number of comparator events

seen by the system when using level sensitive modes. The comparators will continue to function

during Idle mode. If this is not the desired behavior, the comparators should be disabled before

entering Idle. The comparators are always disabled during Power-down mode.

(P2.5) AIN1

(P2.6) AIN2

(P2.4) AIN0

(P2.7) AIN3

RFB1

RFB0

RFA1

RFA0

CSB0

CSB1

CSA0

CSA1

CMPB (P4.7)

CMPA (P4.6)

CMB0

CMB1

CMB2

CMA0

CMA1

CMA2

CFB

CFA

Interrupt

VAREF

VAREF-Δ

VAREF+Δ

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