AT89LP428 datasheet(103/149 Pages) ATMEL

103 / 149 page

103

3654A–MICRO–8/09

AT89LP428/828

Notes:1. CONB must be cleared to 0 before changing CSB [1 - 0].

2. Debouncing modes require the use of Timer 1 to generate the sampling delay.

Table 18-2.

ACSRB

– Analog Comparator B Control and Status Register

ACSRB = 9FH

Reset Value = 1100 0000B

Not Bit Addressable

CSB1

CSB0

CONB

CFB

CENB

CMB2

CMB1

CMB0

Bit

543

Symbol

Function

CSB

[1 - 0]

Comparator B Positive Input Channel Select(1)

CSB1

CSB0

B+ Channel

AIN0 (P2.4)

AIN1 (P2.5)

AIN2 (P2.6)

AIN3 (P2.7)

CONB

Comparator B Input Connect. When CONB = 1, the analog input pins are connected to the comparator. When

CONB = 0 the analog input pins are disconnected from the comparator. CONB must be cleared to 0 before changing

CSB [1 - 0] or RFB [1 - 0].

CFB

Comparator B Interrupt Flag. Set when the comparator output meets the conditions specified by the CMB [2 - 0] bits and

CENB is set. The flag must be cleared by software. The interrupt may be enabled/disabled by setting/clearing bit 6 of IE.

CENB

Comparator B Enable. Set this bit to enable the comparator. Clearing this bit will force the comparator output low and

prevent further events from setting CFB. When CENB = 1, the analog input pins, P2.4 - P2.7, have their digital inputs

disabled if they are configured in input-only mode.

CMB

[2 - 0]

Comparator B Interrupt Mode

CMB2

CMB1

CMB0

Interrupt Mode

000

Negative (Low) level

001

Positive edge

Toggle with debouncing(2)

011

Positive edge with debouncing(2)

100

Negative edge

101

Toggle

110

Negative edge with debouncing(2)

111

Positive (High) level

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