AT89LP428 datasheet(98/149 Pages) ATMEL

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3654A–MICRO–8/09

AT89LP428/828

18. Dual Analog Comparators

The AT89LP428/828 provides two analog comparators. The analog comparators have the fol-

lowing features:

• Internal 3-level Voltage Reference

•Multiple Shared Analog Input Channels

• Selectable Interrupt Conditions

– High- or Low-level

–Rising- or Falling-edge

–Output Toggle

•Hardware Debouncing Modes

A block diagram of the dual analog comparators with relevant connections is shown in Figure

18-1. Input options allow the comparators to function in a number of different configurations as

shown in Figure 18-3. Comparator operation is such that the output is a logic “1” when the posi-

tive input is greater than the negative input. Otherwise, the output is a zero. Setting the CENA

(ACSRA.3) and CENB (ACSRB.3) bits enable Comparator A and B, respectively. The user must

also set the CONA (ACSRA.5) or CONB (ACSRB.5) bits to connect the comparator inputs

before using a comparator. When a comparator is first enabled, the comparator output and

Table 17-4.

SPSR – SPI Status Register

SPSR Address = E8H

Reset Value = 0000 X000B

Not Bit Addressable

SPIF

WCOL

MODF

TXE

–

SSIG

DISSOENH

Bit

76543

210

Symbol

Function

SPIF

SPI Transfer Complete Interrupt Flag. When a serial transfer is complete, the SPIF bit is set by hardware and an interrupt

is generated if ESP = 1. The SPIF bit may be cleared by software or by reading the SPI status register followed by

reading/writing the SPI data register.

WCOL

Write Collision Flag. The WCOL bit is set by hardware if SPDR is written while the transmit buffer is full. The ongoing

transfer is not affected. WCOL may be cleared by software or by reading the SPI status register followed by

reading/writing the SPI data register.

MODF

Mode Fault Flag. MODF is set by hardware when a master mode collision is detected (MSTR = 1, SSIG = 0 and SS = 0)

and an interrupt is generated if ESP= 1. MODF must be cleared by software.

TXE

Transmit Buffer Empty Flag. Set by hardware when the transmit buffer is loaded into the shift register, allowing a new byte

to be loaded. TXE must be cleared by software. When ENH = 1 and ESP = 1, TXE will generate an interrupt.

SSIG

Slave Select Ignore. If SSIG = 0, the SPI will only operate in slave mode if SS (P1.4) is pulled low. When SSIG = 1, the

SPI ignores SS in slave mode and is active whenever SPE (SPCR.6) is set. When MSTR = 1 and SSIG = 0, SS is

monitored for master mode collisions. Setting SSIG = 1 will ignore collisions on SS. P1.4 may be used as a regular I/O

pin when SSIG = 1.

DISSO

Disable slave output bit. When set, this bit causes the MISO pin to be tristated so that more than one slave device can

share the same interface without multiple SS lines. Normally, the first byte in a transmission could be the slave address

and only the selected slave should clear its DISSO bit.

ENH

TX Buffer Interrupt Enable. When ENH = 1, TXE will generate an SPI interrupt if ESP = 1. When ENH = 0, TXE does not

generate an interrupt.

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