MCP4017 datasheet(47/66 Pages) MICROCHIP

47 / 66 page

DS22147A-page 47

MCP4017/18/19

7.0

DESIGN CONSIDERATIONS

In the design of a system with the MCP4017/18/19

devices, the following considerations should be taken

into account. These are:

• The Power Supply

• The Layout

In the design of a system with the MCP4017/18/19

devices, the following considerations should be taken

into account:

• Power Supply Considerations

• Layout Considerations

7.1

Power Supply Considerations

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 7-1 illustrates an

appropriate bypass strategy.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close to the device power pin (VDD) as possible (within

4mm).

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, VDD and

VSS should reside on the analog plane.

FIGURE 7-1:

Typical Microcontroller

Connections.

7.2

Layout Considerations

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially

masking

the

MCP4017/18/19’s

performance. Careful board layout will minimize these

effects and increase the Signal-to-Noise Ratio (SNR).

Bench testing has shown that a multi-layer board

utilizing a low-inductance ground plane, isolated inputs,

isolated outputs and proper decoupling are critical to

achieving the performance that the silicon is capable of

providing. Particularly harsh environments may require

shielding of critical signals.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

7.2.1

RESISTOR TEMPCO

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-11,

Figure 2-29, Figure 2-47, and Figure 2-65.

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is RAB resistance.

VDD

VSS

0.1 µF

SCL

SDA

MCP4017 датащи(PDF) 47 Page - Microchip Technology

MCP4017 датащи(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66

датащи скачать

ссылки URL