MCP4017 datasheet(34/66 Pages) MICROCHIP

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MCP4017/18/19

DS22147A-page 34

5.2

I2C Bit Definitions

I2C bit definitions include:

• Start Bit

• Data Bit

• Acknowledge (A) Bit

• Repeated Start Bit

• Stop Bit

• Clock Stretching

Figure 5-8 shows the waveform for these states.

5.2.1

START BIT

The Start bit (see Figure 5-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “High”.

FIGURE 5-2:

Start Bit.

5.2.2

DATA BIT

The SDA signal may change state while the SCL signal

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 5-3).

FIGURE 5-3:

Data Bit.

5.2.3

ACKNOWLEDGE (A) BIT

The A bit (see Figure 5-4) is a response from the Slave

device to the Master device. Depending on the context

of the transfer sequence, the A bit may indicate

different things. Typically the Slave device will supply

an A response after the Start bit and 8 “data” bits have

been received. The A bit will have the SDA signal low.

FIGURE 5-4:

Acknowledge Waveform.

If the Slave Address is not valid, the Slave Device will

issue a Not A (A). The A bit will have the SDA signal

high.

If an error condition occurs (such as an A instead of A)

then an START bit must be issued to reset the

command state machine.

TABLE 5-1:

MCP4017/18/19 A / A

RESPONSES

5.2.4

REPEATED START BIT

The Repeated Start bit (see Figure 5-5) indicates the

current

Master

Device

wishes

continue

communicating with the current Slave Device without

releasing the I2C bus. The Repeated Start condition is

the same as the Start condition, except that the

Repeated Start bit follows a Start bit (with the Data bits

+ A bit) and not a Stop bit.

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

FIGURE 5-5:

Repeat Start Condition

Waveform.

SDA

SCL

1st Bit

2nd Bit

SDA

SCL

1st Bit

2nd Bit

SDA

SCL

Event

Acknowledge

Bit Response

Comment

General Call

Slave Address

valid

Slave Address

not valid

Bus Collision

N.A.

I2C Module Resets,

or a “Don’t Care” if

the collision occurs

on the Masters

“Start bit”.

Note 1: A bus collision during the Repeated Start

condition occurs if:

• SDA is sampled low when SCL goes

from low to high.

• SCL goes low before SDA is asserted

low. This may indicate that another mas-

ter is attempting to transmit a data "1".

SDA

SCL

Sr = Repeated Start

1st Bit

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