PCA2003USLASH10ACSLASH1 datasheet(16/21 Pages) NXP

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PCA2003_2

Product data sheet

Rev. 02 — 21 July 2009

16 of 21

NXP Semiconductors

PCA2003

32 kHz watch circuit with programmable adaptive motor pulse

Characteristics

[1]

P1 + ... + P4 + N1 + N2 (see Section 7.2).

[2]

RL and CL are a load resistor and load capacitor, externally connected to pad RESET.

Table 10.

Characteristics

VDD = 1.55 V; VSS =0V; fosc = 32.768 kHz; Tamb =25 °C; quartz crystal: RS =40kΩ, C1 = 2 fF to 3 fF, CL = 8.2 pF; unless

otherwise speciﬁed.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Supply

VDD

supply voltage

normal operating mode;

Tamb = −10 °C to +60 °C

1.1

1.55

3.60

∆VDD

supply voltage variation

∆V/∆t=1V/µs

0.25

IDD

supply current

between motor pulses

120

between motor pulses

at VDD = 3.5 V

120

180

Tamb = −10 °C to +60 °C

200

stop mode;

pad RESET connected to

VDD

100

135

Motor output

Vsat

saturation voltage

Rmotor =2kΩ;

Tamb = −10 °C to +60 °C

[1] -

150

200

Zo(sc)

output impedance

(short circuit)

between motor pulses;

Imotor <1mA

200

300

Ω

Oscillator

Vstart

start voltage

1.1

transconductance

Vi(osc) ≤ 50 mV (p-p)

µS

tstartup

start-up time

0.3

0.9

∆f/f

frequency stability

∆VDD = 100 mV

0.05

0.20

ppm

CL(itg)

integrated load

capacitance

4.3

5.2

6.3

Rpar

parasitic resistance

allowed resistance between

adjacent pads

--M

Ω

Pad RESET

output frequency

VO(dif)

differential output

voltage

RL =1MΩ; CL =10pF

[2] 1.4

rise time

RL =1MΩ; CL =10pF

[2] -1

µs

fall time

RL =1MΩ; CL =10pF

[2] -1

µs

Ii(AV)

average input current

pad RESET connected to

VDD or VSS

1020nA

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