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PCA2003U/10AC/1 датащи(PDF) 14 Page - NXP Semiconductors |
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PCA2003U/10AC/1 датащи(HTML) 14 Page - NXP Semiconductors |
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14 / 21 page ![]() PCA2003_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 21 July 2009 14 of 21 NXP Semiconductors PCA2003 32 kHz watch circuit with programmable adaptive motor pulse • State 1: quartz crystal oscillator frequency divided by 1024; state 1 starts with a pulse to VP and ends with a second pulse to VP • State 2: inhibition time has a value of n × 0.122 ms. A signal with periodicity of 31.25 ms + n × 0.122 ms appears at pad RESET and as current modulation at pad VDD (see Figure 11 and Figure 12) 7.11 Customer testing Connecting pad RESET to VSS activates the test mode. In this test mode, the motor output frequency is 8 Hz; the duty cycle reduction and battery check occurs every second, instead of every 4 minutes. Fig 11. Output waveform at pad RESET for instruction state 2 VDD(nom): nominal supply voltage. Fig 12. Supply voltage modulation for starting and stopping of instruction state 2 mgw355 VDD VSS 31.25 ms + inhibition time VO(dif) VDD VP(prog)(start) VP(mod) VP(prog)(stop) t1 tp(start) t0 VSS VDD(nom) mgu719 tp(stop) |
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