TSB12C01APZ datasheet(25/59 Pages) TI

25 / 59 page

3–9

information to the TSB12C01A, the phy register-information-receive (PhyRRx) interrupt is set. The register

is at address 24h and is read/write. Its initial value is 0000_0000h. All gap counts (set in the phy device

registers) on all nodes of a 1394 bus must be identical. This can be accomplished by using the phy

configuration packets to set a specific gap count or by using two bus resets, which resets the gap counts

to the default 3Fh. See Section 4.6 for the format of the phy configuration packets.

Table 3–8. Phy-Chip Access Register

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

RdPhy

Read phy-chip

When RdPhy is set, the TSB12C01A sends a read register request with

address equal to phyRgAd to the phy interface. This bit is cleared when

the request is sent.

WrPhy

Write phy-chip

When WrPhy is set, the TSB12C01A sends a write register request

with an address equal to phyRgAd on to the phy interface. This bit is

cleared when the request is sent.

2–3

Reserved

4–7

PhyRgAd

Phy-chip-register

address

PhyRgAd is the address of the phy-chip register that is to be accessed.

8–15

PhyRgData

Phy-chip-register

data

PhyRgData is the data to be written to the phy-chip register indicated

in PhyRgAd.

16 – 19

Reserved

20 – 23

PhyRxAd

Phy-chip-register-

received address

PhyRxAd is the address of the register from which PhyRxData came.

24 – 31

PhyRxData

Phy-chip-register-

received data

PhyRxData contains the data from register addressed by PhyRxAd.

3.2.9

Asynchronous Transmit-FIFO (ATF) Status Register

The ATF status register allows access to the registers that control or monitor the ATF. The register is at

address 30h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value

is 0000_0000h.

Table 3–9. ATF Status Register

BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Full

ATF full flag

When Full is set, the FIFO is full. Write operations are ignored.

AlF

ATF almost-full flag

When AlF is set, the FIFO can accept one more write.

2–3

Reserved

4AV

ATF-4-available flag

When 4AV is set, the FIFO has space available for at least four

quadlets.

5–13

Reserved

AlE

ATF-almost-empty flag

When AlE is set, the FIFO has only one quadlet in it.

Empty

ATF-empty flag

When Empty is set, the FIFO is empty.

16 – 18

Reserved

Clr

ATF-clear control bit

When Clr is set by software/firmware, the FIFO is cleared of all

entries.

20 – 22

Reserved

23 – 31

Size

ATF-size control bits

Size is equal to the ATF size number in quadlets.

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