TSB12C01APZ datasheet(53/59 Pages) TI

53 / 59 page

7–5

7.6.1

Status Request

The definition of the bits in the status transfer is shown in Table 7–9.

Table 7–9. Status-Request Functions (Length of Stream: 16 Bits)

BIT(s)

NAME

DESCRIPTION

Arbitration Reset

Gap

The arbitration-reset gap bit indicates that the phy interface has detected that the bus

has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995

standard). This bit is used by the TSB12C01A in its busy/retry state machine.

Fair Gap

The fair-gap bit indicates that the phy interface has detected that the bus has been idle

for a fair-gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used

by the TSB12C01A to detect the completion of an isochronous cycle.

Bus Reset

The bus reset bit indicates that the phy interface has entered the bus reset state.

phy Interrupt

The phy interrupt bit indicates that the phy interface is requesting an interrupt to the host.

4–7

Address

The address bits hold the address of the phy register whose contents are transferred

to the TSB12C01A.

8–15

Data

The data bits hold the data that is to be sent to the TSB12C01A.

Normally, the phy interface sends just the first four bits of data to the TSB12C01A. These bits are used by

the TSB12C01A state machine. However, if the TSB12C01A initiates a read request (through a request

transfer), then the phy interface sends the entire status packet to the TSB12C01A. Additionally, the phy

interface sends the contents of the register to the TSB12C01A when it has some important information to

pass on. Currently, the only condition where this occurs is after the self-identification process when the phy

interface needs to inform the TSB12C01A of its new node address (physical ID register).

There may be times when the phy interface wants to start a second status transfer. The phy interface first

has to wait at least one clock cycle with the CTL lines idle before it can begin a second transfer.

7.6.2

Transmit

When the TSB12C01A wants to transmit information, it first requests access to the bus through an LREQ

signal. Once the phy interface receives this request, it arbitrates to gain control of the bus. When the phy

interface wins ownership of the serial bus, it grants the bus to the TSB12C01A by asserting the transmit state

on the CTL terminals for at least one SCLK cycle. The TSB12C01A takes control of the bus by asserting

either hold or transmit on the CTL lines. Hold is used by the TSB12C01A to keep control of the bus when

it needs some time to prepare the data for transmission. The phy interface keeps control of the bus for the

TSB12C01A by asserting a data-on state on the bus. It is not necessary for the TSB12C01A to use hold

when it is ready to transmit as soon as bus ownership is granted.

When the TSB12C01A is prepared to send data, it asserts transmit on the CTL lines as well as sends the

first bits of the packet on the D0 – D7 lines (assuming 400 Mb/s). The transmit state is held on the CTL

terminals until the last bits of data have been sent. The TSB12C01A then asserts idle on the CTL lines for

one clock cycle after which it releases control of the interface.

However, there are times when the TSB12C01A needs to send another packet without releasing the bus.

For example, the TSB12C01A may want to send consecutive isochronous packets or it may want to attach

a response to an acknowledgment. To do this, the TSB12C01A asserts hold instead of idle when the first

packet of data has been completely transmitted. Hold, in this case, informs the phy interface that the

TSB12C01A needs to send another packet without releasing control of the bus. The phy interface then waits

a set amount of time before asserting transmit. The TSB12C01A can then proceed with the transmittal of

the second packet. After all data has been transmitted and the TSB12C01A has asserted idle on the CTL

terminals, the phy interface asserts its own idle state on the CTL lines. When sending multiple packets in

this fashion, it is required that all data be transmitted at the same speed. This is required because the

transmission speed is set during arbitration, and since the arbitration step is skipped, there is no way of

informing the network of a change in speed.

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