TSB12C01APZ datasheet(13/59 Pages) TI

номер детали	TSB12C01APZ

подробное описание детали	High-Speed Serial-Bus Link-Layer Controller

PDF	59 Pages

Scroll/Zoom	100%

производитель	TI [Texas Instruments]

домашняя страница	http://www.ti.com

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13 / 59 page

2–1

2 Architecture

2.1

Functional Block Diagram

The functional block architecture of the TSB12C01A is shown in Figure 2–1.

Transmitter

Cycle Timer

Cycle Monitor

CRC

Receiver

Configuration Registers

GRF

ITF

ATF

Figure 2–1. TSB12C01A Block Diagram

2.1.1

Physical Interface

The physical (phy) interface provides phy-level services to the transmitter and receiver. This includes

gaining access to the serial bus, sending packets, receiving packets, and sending and receiving

acknowledge packets.

The phy interface module also interfaces to the phy chip and conforms to the phy-link interface specification

described in Annex J of the IEEE 1394-1995 standard (refer to Section 7 of this document for more

information).

2.1.2

Transmitter

The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus

packets to be transmitted through the phy interface. When data is present at the ATF interface to the

transmitter, the TSB12C01A phy interface arbitrates for the serial bus and sends a packet. When data is

present at the ITF interface to the transmitter, the TSB12C01A arbitrates for the serial bus during the next

isochronous cycle. The transmitter autonomously sends the cycle-start packets when the chip is a cycle

master.

TSB12C01APZ датащи(PDF) 13 Page - Texas Instruments