HC210 datasheet(32/228 Pages) ALTERA

32 / 228 page

2–24

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

The programmable drive strengths available vary depending on the I/O

standard used. The options are listed in Table 2–12.

Memory interface IOEs support both non-calibrated and calibrated

on-chip series termination. 50- and 25-

Ω on-chip series termination is

available for 3.3-, 2.5-, or 1.8-V I/O standards. 50-

Ω on-chip series

termination is available for 1.5- or 1.2-V I/O standards (pending

characterization).

If on-chip series termination is enabled, programmable drive

strength support is not available.

HC240

1,020-pin FineLine BGA

1,508-pin FineLine BGA

Table 2–11. DQS and DQ Bus Mode Support (Part 2 of 2)

Device

Package

Number of ×4

Groups

Number of ×8/×9

Groups

Number of

×16/×18 Groups

Number of

×32/×36 Groups

Table 2–12. Programmable Drive Strength Support for Memory Interface

IOEs

I/O Standard

Programmable Drive Strength Options (mA)

3.3-V LVTTL

4, 8, 12, 16, 20, 24

3.3-V LVCMOS

4, 8, 12, 16, 20, 24

2.5-V LVTTL/LVCMOS

4, 8, 12, 16

1.8-V LVTTL/LVCMOS

2, 4, 6, 8, 10, 12

1.5-V LVCMOS

2, 4, 6, 8

SSTL-2 class I

8, 12

SSTL-2 class II

16, 20, 24

SSTL-18 class I

4, 6, 8, 10, 12

SSTL-18 class II

8, 16, 18, 20

1.8-V HSTL class I

4, 6, 8, 10, 12

1.8-V HSTL class II

16, 18, 20

1.5-V HSTL class I

4, 6, 8, 10, 12

1.5-V HSTL class II

16, 18, 20

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