HC210 datasheet(28/228 Pages) ALTERA

28 / 228 page

2–20

Altera Corporation

Preliminary

September 2008

HardCopy Series Handbook, Volume 1

Figure 2–6. I/O Type Support in HC240 Devices

Notes (1), (2)

Notes to Figures 2–4 through 2–6:

(1)

In addition to supporting external memory interfaces, memory interface IOEs have the same features as general

purpose IOEs. In addition to supporting high-speed I/O interfaces, high-speed IOEs have the same features as

general purpose IOEs, except for the PCI clamping diode and LVPECL clock input support.

(2)

This is a top view of the silicon die which corresponds to a reverse view for flip-chip packages. It is a graphical

representation only.

When planning I/O placement for designs targeting

HardCopy II devices, care should be taken to ensure the same

I/O standards are supported in the same HardCopy II I/O

banks as in the Stratix II I/O banks.

General Purpose IOE

The general purpose IOEs in HC210 and HC220 devices are located on the

right side and at the bottom of the device. The general purpose IOEs in

HC230 devices are located on the right side of the device. (Directions are

based on a top view of the silicon die.) HC240 devices do not have general

purpose IOEs. The general purpose IOE functionality is supported in the

memory interface IOEs for these devices. The high-speed IOEs also

Bank 4

Memory Interface IOEs

Bank 7

Memory Interface IOEs

Bank 8

Memory Interface IOEs

I/O banks 3 & 4 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS, SSTL-2, SSTL-18, 1.8-V

HSTL, 1.5-V HSTL & PCI/PCI-X I/O standards.

I/O banks 7 & 8 support 3.3-V, 2.5-V, 1.8-V LVTTL/

LVCMOS, 1.5-V LVCMOS & PCI/PCI-X I/O standards.

Bank 3

Memory Interface IOEs

Bank 2

High-Speed IOEs

Bank 1

High-Speed IOEs

Bank 5

High-Speed IOEs

Bank 6

High-Speed IOEs

PLL 1

PLL 2

PLL 4

PLL 3

I/O Banks 5 & 6 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &

HyperTransport Technology

I/O Banks 1 & 2 Support 3.3-,

2.5- & 1.8-V LVTTL/LVCMOS,

1.5-V LVCMOS, LVDS &

HyperTransport Technology

CLK, PLL_FB input pins & PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

CLK, PLL_FB input pins SSTL-2, SSTL-18, 1.8-V HSTL, 1.5-V HST,

& PLL_OUT output

pins support differential SSTL, differential HSTL,

LVDS & HyperTransport technology. CLK & PLL_FB

pins support LVPECL. DQS input pins support

differential SSTL and differential HSTL I/O standards.

PLL 5

PLL 11

Bank 11 Bank 9

PLL 6

PLL 12

Bank 12 Bank 10

PLL 10

PLL 9

PLL 7

PLL 8

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