HC210 datasheet(67/228 Pages) ALTERA

67 / 228 page

Altera Corporation

4–25

September 2008

Maximum Output Clock Rates

Maximum

Output Clock

Rates

Tables 4–35 and 4–36 show the maximum output toggle rates of

HardCopy II I/O's for all available drive strengths.

HyperTransport

—

320

—

320

—

320

—

MHz

Notes to Table 4–34:

(1)

The PCI clamping diode is only supported on the top and bottom I/O pins.

(2)

For HC210W, differential HSTL/SSTL input is supported on the top clock pins, the

DQS pins on the top I/O banks and

top/bottom

PLL_FB input pins.

(3)

These numbers are preliminary and pending further silicon characterization.

Table 4–34. HardCopy II Maximum Input Clock Rates of HC210W Devices

Note (3) (Part 2 of 2)

I/O Standard

Memory

Interface

IOEs

High

Speed

IOEs

General

Purpose

IOEs

CLK

[0..3,

8..11]

CLK

[4..7,

12..15]

FPLL_C

PLL_FB

Unit

Table 4–35. HardCopy II Maximum Output Clock Rate of HC210, HC220, HC230 and HC240 Devices

Note (1) (Part 1 of 5)

I/O Standard

Drive

Strength

Memory

Interface

IOEs

High

Speed

IOEs

General Purpose

IOEs

CLK [0,

2, 8,

10] (2)

CLK

[4..7,

12..15]

PLL_OUT

Unit

Bottom

Column

Right

Row

3.3-V LVTTL

4 mA

225

MHz

8 mA

355

MHz

12 mA

475

MHz

16 mA

594

—

594

MHz

20 mA

700

—

700

MHz

24 mA (3)

794

—

794

MHz

3.3-V LVCMOS

4 mA

250

MHz

8 mA

480

MHz

12 mA

710

—

710

MHz

16 mA

925

—

925

MHz

20 mA

985

—

985

MHz

24 mA (3)

1040

—

1040

MHz

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