SC417 datasheet(23/29 Pages) SEMTECH

23 / 29 page

SC417/SC427

Applications Information (continued)

One simple way to solve this problem is to add trace resis-

tance in the high current output path. A side effect of

adding trace resistance is output decreased load

regulation.

ESR Requirements

A minimum ESR is required for two reasons. One reason is

to generate enough output ripple voltage to provide

10mVp-p at the FB pin (after the resistor divider) to avoid

double-pulsing.

The second reason is to prevent instability due to insuffi-

cient ESR. The on-time control regulates the valley of the

output ripple voltage. This ripple voltage is the sum of the

two voltages. One is the ripple generated by the ESR, the

other is the ripple due to capacitive charging and dis-

charging during the switching cycle. For most applica-

tions the minimum ESR ripple voltage is dominated by the

output capacitors, typically SP or POSCAP devices. For

stability the ESR zero of the output capacitor should be

lower than approximately one-third the switching fre-

quency. The formula for minimum ESR is shown by the

following equation.

OUT

MIN

For applications using ceramic output capacitors, the ESR

is normally too small to meet the above ESR criteria. In

these applications it is necessary to add a small virtual ESR

network composed of two capacitors and one resistor, as

shown in Figure 14. This network creates a ramp voltage

across C

, analogous to the ramp voltage generated across

the ESR of a standard capacitor. This ramp is then capaci-

tively coupled into the FB pin via capacitor C

COUT

Low-

side

High-

side

Figure 14 — Virtual ESR Ramp Current

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is limited by the fixed 250ns (typical)

minimum off-time of the one-shot. When working with

low input voltages, the duty-factor limit must be calcu-

lated using worst-case values for on and off times.

The duty-factor limitation is shown by the next equation.

)

MAX

(

OFF

)

MIN

(

)

MIN

(

DUTY

The inductor resistance and MOSFET on-state voltage

drops must be included when performing worst-case

dropout duty-factor calculations.

System DC Accuracy (V

OUT Controller)

Three factors affect V

OUT

accuracy: the trip point of the FB

error comparator, the ripple voltage variation with line

and load, and the external resistor tolerance. The error

comparator offset is trimmed so that under static condi-

tions it trips when the feedback pin is 500mV, 1%.

The on-time pulse from the SC417/SC427 in the design

example is calculated to give a pseudo-fixed frequency of

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