SC417/SC427

6

Electrical Characteristics (continued)

Parameter

Conditions

Min

Typ

Max

Units

Fault Protection

Valley Current Limit

R

ILIM

= 5.9k Ω

6

8

10

A

I

LIM

Source Current

10

μA

I

LIM

Comparator Offset

with respect to AGND

-10

0

+10

mV

Output Under-Voltage Fault

V

FB

with respect to internal 500mV reference,

8 consecutive clocks

-25

%

V

FB

with respect to internal 500mV reference

+10

%

Over-Voltage Protection Threshold

V

FB

with respect to internal 500mV reference

+20

%

5μs

10°C hysteresis

150

°C

Logic Inputs/Outputs

Logic Input High Voltage

EN/PSV, ENL

2.0

V

Logic Input Low Voltage

EN/PSV, ENL

0.4

V

EN/PSV Input Bias Current

EN/PSV= V5V or AGND

-10

+10

μA

ENL Input Bias Current

V

IN

= 28V

11

18

μA

FBL, FB Input Bias Current

FBL, FB = V5V or AGND

-1

+1

μA

Linear Regulator (LDO)

FBL Accuracy

VLDO load = 10mA

0.735

0.75

0.765

V

LDO Current Limit

Start-up and foldback, V

IN

= 12V

85

mA

operating current limit, V

IN

= 12V

135

200

-140

+140

mV

-450

+450

mV

VLDO to VOUT Switch-over Resistance

V

OUT

= +5V

2

Ω

from V

IN

to V

VLDO

, V

VLDO

= +5V, I

VLDO

= 100mA

1.2

V

Notes:

(1)

V

IN

UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.

(2)

Guaranteed by design.

(3)

The switch-over threshold is the maximum voltage differential between the VLDO and VOUT pins which ensures that VLDO will internally

switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures

that VLDO will not switch-over to VOUT.

(4)

The LDO drop out voltage is the voltage at which the LDO output drops 2% below the nominal regulation point.