ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

11

FUNCTIONAL DESCRIPTION

The ML5800 enables the design and manufacture of low-cost, small yet high-performance digital RF transceivers in the

relatively interference-free 5.8GHz ISM band. Frequency Shift Keying (FSK) is a constant-envelope modulation, which

allows the use of high-efficiency class C power amplifier (such as the ML5803) resulting in longer battery life.

Integrated in the ML5800 is a dual-conversion low-IF receiver with completely integrated filters, all frequency generation

circuits, and transmit circuits. On-chip regulators protect critical circuits from power-supply noise and allow for

consistent performance over the supply voltage range.

The ML5800 transmits and receives 1.536Mbps FSK data in the 5.725 to 5.850GHz ISM band. The high data rate

allows for direct sequence spread spectrum coding, which increases interference rejection and input sensitivity at the

cost of reduced effective data rate. For example, a 15-chip spreading sequence results in 11.7dB of processing gain

and a ‘raw’ data rate of 102.4kbps.

The ML5800 contains a dual-conversion low-IF receiver. The first IF frequency of 1.9GHz gives an image response,

also at 1.9GHz. An off-chip filter is needed to protect the receiver from this image and from IF feedthrough. The second

IF frequency of 1.024MHz results in an image response in an adjacent channel. The quadrature image-reject mixer and

low IF filter combine to achieve a typical image rejection of 35dB. All IF filtering and demodulation are performed on

chip using active filtering, centered at 1.024MHz. A matched bit-rate filter and data slicer follow the demodulator and

provide sliced data at the DOUT pin. Buffered analog (unsliced) data is available on the AOUT_TPC pin.

The ML5800 transmitter uses a fractional-N PLL and two-port closed loop modulation to accurately impress the FSK

signal on the 5.8GHz carrier. Closed loop modulation techniques allow for continuous transmission or reception of data

without significant frequency drift, making the ML5800 ideal for wireless streaming media applications. A lock-detect

circuit monitors the state of the PLL loop. When the PLL is out of lock the transmitter output is disabled.

The frequency generation circuits are comprised of a fully integrated 3.9GHz VCO local oscillator (LO), dividers, a

phase comparator, and a charge pump for a PLL frequency synthesizer. A fractional-N PLL applies the low frequency

data modulation onto the LO. The LO is halved to generate accurate quadrature signals at 1.9GHz for the second LO.

The LO PLL is programmed via the three-wire serial bus (CLK, DATA, EN). There is no error checking of the program

data. This bus is functional, and register contents are preserved in STANDBY mode.

Filter

Alignment

PLL

Divider

TXO

5.8GHz

Output

Quadrature

Downmixers

3.9 GHz

VCO

PLL Loop

Filter

Digital

Output

Transmit

Data

Input

Ref.

Divider

Control

Registers

Serial

Control

Bus

RSSI

P.D.

Frequenc

Referenc

Mode

Control

Control

lines

Quadrature

Generation

Two-port

Modulator

F

to

V

RSSI

RXI

5.8GHz

Input

PAON

RXON

XCEN

DATA

CLK

EN

VTUNE

QPO

Transmit

Mixer

DIN

FREF

DOUT

Receive

Signal

Strength

Indicator

Receiver

Mixer

Analog

Output

AOUT_TPC

Figure 2: ML5800 Block Diagram