ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

22

REGISTER 2 BIT DESCRIPTIONS

DATA BIT

NAME

DESCRIPTION

USE

B15 (MSB) / DB13

TMODE

B14 / DB12

CFB6

B13 / DB11

CFB5

B12 / DB10

CFB4

B11 / DB9

CFB3

B10 / DB8

CFB2

B9 / DB7

CFB1

B8 / DB6

CFB0

Filter Alignment Control Bits

See Table 21

B7 / DB5

DTM2

B6 / DB4

DTM1

B5 / DB3

DTM0

Digital Test Control Bits

See Table 20

B4 / DB2

ATM2

B3 / DB1

ATM 1

B2 / DB0

ATM 0

Analog Test Control Bits

See Table 19

B1 / ADB1

ADR1

MSB Address Bit

ADR1 = 1

B0 (LSB) / ADB0

ADR0

LSB Address Bit

ADR0 = 0

Table 18: Register 2 – Test Mode Access Register

ATM<2:0>

Analog Test Control Bits:

The performance of the ML5800 is not specified in these test modes. Although primarily

intended for IC test and debug, they also can help in debugging the radio system. The default (power-up) state of these

bits is ATM<2:0> = <0,0,0>. When a non-zero value is written to the field, the RSSI and AOUT_TPC pins become

analog test access ports, giving access to the outputs of key signal processing stages in the transceiver. During normal

operation, the ATM field must be set to zero (see Table 19).

ATM2

ATM1

ATM0

RSSI

AOUT

0

0

0

RSSI

Set by AOUT bit

0

0

1

Data Filter input +

Data Filter input -

0

1

0

I IF Filter Output

Q IF Filter Output

0

1

1

Q IF Filter – Input

Q IF Filter + Input

1

0

0

I IF Filter – Input

I IF Filter + Input

1

0

1

Data Filter + Output

Data Filter –Output

1

1

0

I IF Limiter Output

Q IF Limiter Output

1

1

1

1.67V Voltage Reference

VCO Modulation Port Input

Table 19: Analog Test Control Bits