ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

5

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TRANSMITTER

Output Impedance

at TXO

22.5+j3

Ω

Matched into 50ohms, 25C and 3.3V

-4

0

3

TX buffer output power at 5.8GHz

Matched into 50ohms, over operating

temperature and voltage range

-7

0

3

dBm

Transmit Modulation Deviation

TXO pin See Figure 6

±512

kHz

TX Data Filter 3dB Bandwidth

1.4

MHz

TX spurious

-25

dBc

TX Image

-20

dBc

INTERFACE LOGIC LEVELS

Input pins (DIN, XCEN, RXON, DATA, CLK, EN)

Input high voltage

VDD*0.7

VDD+0.4

V

Input low voltage

-0.4

VDD*0.3

V

Input bias current

All states

-5

5

μA

Input capacitance

1MHz test frequency

4

pF

Output pins (AOUT_TPC, PAON, DOUT)

AOUT open-drain voltage

0.4

V

PAON (PA control) output high voltage

Sourcing 5.0mA

VDD-0.4

V

PAON (PA control) output low voltage

Sinking 5.0mA

0.4

V

PAON source/sink current

±5.0

±8.0

mA

DOUT (data output) output high voltage

Sourcing 0.1mA

VDD–0.4

V

DOUT (data output) output low voltage

Sinking 0.1mA

0.4

V

3 WIRE SERIAL BUS TIMING

CLK input rise time (note 1)

15

ns

CLK input fall time (note 1)

15

ns

CLK period

50

ns

EN pulse width

200

ns

Delay from last clock rising edge to rise

of EN

15

ns

EN setup time to ignore next rising CLK

15

ns

DATA-to-CLK setup time

15

ns

DATA-to-CLK hold time

See Figure 5

15

ns

Note 1: Serial I/O clock maximum rise and fall times are based on the minimum clock period. Longer rise and fall times

can be accommodated for slower clocks provided the rise and fall times remain less than 20% of the clock period and

serial I/O clock rise and fall times are limited to an absolute maximum of 100ns.