ML5800

DS5800-F-04

FINAL DATASHEET

JULY 2006

21

REGISTER 1 BIT DESCRIPTIONS

DATA BIT

NAME

DESCRIPTION

USE

B15 (MSB) / DB13

N9

B14 / DB12

N8

B13 / DB11

N7

B12 / DB10

N6

B11 / DB9

N5

B10 / DB8

N4

B9 / DB7

N3

B8 / DB6

N2

B7 / DB5

N1

B6 / DB4

N0

PLL Integer Part - N

N = MOD [Floor ((F/4.608) – 0.512 – ((P+11)/18)), 1024]

B5 / DB3

P3

B4 / DB2

P2

B3 / DB1

P1

B2 / DB0

P0

PLL Fractional Part – P

P= MOD [Round (F/0.512 – 11), 9]

B1 / ADR1

ADR1

MSB Address Bit

ADR1 = 0

B0 (LSB) / ADR0

ADR0

LSB Address Bit

ADR0 = 1

Table 17: Register 1 – Channel Frequency Register

This register sets the channel frequency for the ML5800 transceiver.

The “N” Field is the 10-bit integer part of the division ratio, modulo 1024. There is an implicit MSB in the “B16” position

which is fixed to “1”. Values from 0 (00 0000 0000b) to 1022 (11 1111 1110b) are all valid and correspond to N =1024 to

N = 2046. The 4-bit “P” field is the fractional part of the division ratio, modulo 9. Values from 0 (0000b) to 8 (1000b) are

valid.

The relationship between N and P with a given channel frequency F is:

F = 1.5 * 6.144 * (512 +N/2 + (P+11)/18) MHz

To calculate N and P from the channel frequency, F (in MHz) use these formulae:

N = MOD [Floor ((F/4.608) – 0.512 – ((P+11)/18)), 1024]

P= MOD [Round (F/0.512 – 11), 9]