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CS43L22 датащи(PDF) 38 Page - Cirrus Logic |
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CS43L22 датащи(HTML) 38 Page - Cirrus Logic |
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38 / 68 page ![]() 38 DS792F1 CS43L22 Confidential Draft 10/7/08 7. REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is shown as shaded in the table. All “Reserved” bits must maintain their default value. 7.1 Chip I.D. and Revision Register (Address 01h) (Read Only) 7.1.1 Chip I.D. (Read Only) I.D. code for the CS43L22. 7.1.2 Chip Revision (Read Only) CS43L22 revision level. 7.2 Power Control 1 (Address 02h) 7.2.1 Power Down Configures the power state of the CS43L22. Note: 1. All states of PDN[7:0] not shown in the table are reserved. 76 543 21 0 CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0 CHIPID[4:0] Device 11100 CS43L22 REVID[2:0] Revision Level 000 A0 001 A1 010 B0 011 B1 76 543 21 0 PDN7 PDN6 PDN5 PDN4 PDN3 PDN2 PDN1 PDN0 PDN[7:0] Status 0000 0001 Powered Down - same as setting 1001 1111 1001 1110 Powered Up 1001 1111 Powered Down - same as setting 0000 0001 |
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