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CS43L22 датащи(PDF) 31 Page - Cirrus Logic

номер детали CS43L22
подробное описание детали  Low Power, Stereo DAC w/Headphone & Speaker Amps
PDF  68 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L22 датащи(HTML) 31 Page - Cirrus Logic

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DS792F1
31
CS43L22
Confidential Draft
10/7/08
Note:
*The marked sample rate values are not exact representations of the actual frame clock frequency
They have been truncated to 4 decimal places. The exact value can be calculated by dividing the
MCLK being used by the desired MCLK/LRCK ratio.
Table 1. Serial Port Clocking
4.7
Digital Interface Formats
The serial port operates in standard I²S, Left-Justified, Right-Justified, or DSP Mode digital interface formats
with varying bit depths from 16 to 24. Data is clocked into the DAC on the rising edge of SCLK.
27.0000
8.0000
11
1
1
01
0
12.0000
11
0
1
01
0
24.0000
10
0
1
01
0
32.0000
01
1
1
01
0
*44.1176...
01
0
1110
48.0000
01
0
1
01
0
*11.0294...
11
0
1
11
0
*22.0588...
10
0
1110
16.0000
10
1
1
01
0
MCLK
(MHz)
Sample Rate,
Fs (kHz)
SPEED[1:0]
(AUTO=’0’b)
32kGROUP
VIDEOCLK
RATIO[1:0]
MCLKDIV2
LRCK
SCLK
MS B
LS B
MS B
LS B
AOUTA
Le ft C h a n n e l
R igh t C han ne l
SDIN
AOUTB
MSB
Figure 12. I²S Format
LRCK
SCLK
MSB
LSB
MSB
LSB
Left Channel
Right Channel
SDIN
MSB
AOUTA
AOUTB
Figure 13. Left-Justified Format
LRCK
SC LK
MS B
LS B
MS B
LS B
Le f t C han ne l
R i g h t C h an n e l
SD IN
AO UTA
AO UTB
Audio W ord Length (AW L)
Figure 14. Right-Justified Format\



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