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CS43L22 датащи(PDF) 17 Page - Cirrus Logic

номер детали CS43L22
подробное описание детали  Low Power, Stereo DAC w/Headphone & Speaker Amps
PDF  68 Pages
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производитель  CIRRUS [Cirrus Logic]
домашняя страница  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L22 датащи(HTML) 17 Page - Cirrus Logic

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DS792F1
17
CS43L22
Confidential Draft
10/7/08
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND; Logic 1 = VL.
11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are
settled.
12. See “Example System Clock Frequencies” on page 62 for typical MCLK frequencies.
Parameters
Symbol
Min
Max
Units
RESET pin Low Pulse Width
(Note 11)
1-
ms
MCLK Frequency (Note 12)
(See “Serial Port Clock-
ing” on page 30)
MHz
MCLK Duty Cycle
45
55
%
Slave Mode
Sample Rate (LRCK)
Fs
(See “Serial Port Clock-
ing” on page 30)
kHz
LRCK Duty Cycle
45
55
%
SCLK Frequency
1/tP
-
64•Fs
Hz
SCLK Duty Cycle
45
55
%
LRCK Setup Time Before SCLK Rising Edge
ts(LK-SK)
40
-
ns
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
th
20
-
ns
Master Mode
Sample Rate (LRCK)
Fs
(See “Serial Port Clock-
ing” on page 30)
Hz
LRCK Duty Cycle
45
55
%
SCLK Frequency
SCLK=MCLK mode
1/tP
-
12.0000
MHz
MCLK=12.0000 MHz
1/tP
-
68•Fs
Hz
all other modes
1/tP
-
64•Fs
Hz
SCLK Duty Cycle
45
55
%
SDIN Setup Time Before SCLK Rising Edge
ts(SD-SK)
20
-
ns
SDIN Hold Time After SCLK Rising Edge
th
20
-
ns
//
//
//
//
//
//
ts(SD-SK)
MSB
MSB-1
LRCK
SCLK
SDIN
ts(LK-SK)
tP
th
Figure 3. Serial Audio Interface Timing



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