CS43L22 datasheet(33/68 Pages) CIRRUS

33 / 68 page

DS792F1

CS43L22

Confidential Draft

10/7/08

Wait at least 100 µs.

The device will be fully powered down after this 100 µs delay. Prior to the removal of the master clock

(MCLK), this delay of at least 100 µs must be implemented after step 3 to avoid premature disruption

of the DAC’s power down sequence.

A disruption in the device’s power down sequence (i.e. removing the MCLK signal before this 100 µs

delay) has consequences on both the headphone and PWM speaker amplifiers: The charge pump may

stop abruptly, causing the headphone amplifiers to drive the outputs up to the +VHP supply. Also, the

last state of each ‘+’ and ‘-’ PWM output terminal before the premature removal of MCLK could randomly

be held at either VP or AGND. When this event occurs, it is possible for each PWM terminal to output

opposing potentials, creating a DC source into the speaker voice coil.

The disruption of the device’s power down sequence may also cause clicks and pops on the output of

the DAC’s as the modulator holds the last output level before the MCLK signal was removed.

MCLK may be removed at this time.

To achieve the lowest operating quiescent current, bring RESET low. All control port registers will be

reset to their default state.

4.11

Required Initialization Settings

Various sections in the device must be adjusted by implementing the initialization settings shown below after

power-up sequence step 3. All performance and power consumption measurements were taken with the

CS43L22 датащи(PDF) 33 Page - Cirrus Logic