CS43L22 datasheet(32/68 Pages) CIRRUS

32 / 68 page

DS792F1

CS43L22

Confidential Draft

10/7/08

4.7.1

DSP Mode

In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on

SDIN. The MSB is input on the first SCLK rising edge after the frame sync rising edge. The right channel

immediately follows the left channel.

4.8

Initialization

The CS43L22 enters a Power-Down state upon initial power-up. The interpolation and decimation filters,

delta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and

switched-capacitor low-pass filters are powered down.

The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac-

cessible once RESET is high and the desired register settings can be loaded per the interface descriptions

in the “Register Description” on page 38.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage reference, FILT+, will begin power-

ing up to normal operation. The charge pump slowly powers up and charges the capacitors. Power is then

applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-

ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the

MCLK/LRCK frequency ratio and normal operation begins.

4.9

Recommended Power-Up Sequence

Hold RESET low until the power supplies are stable.

Bring RESET high.

The default state of the “Power Ctl. 1” register (0x02) is 0x01. Load the desired register settings while

keeping the “Power Ctl 1” register set to 0x01.

Load the required initialization settings listed in Section 4.11.

Apply MCLK at the appropriate frequency, as discussed in Section 4.6. SCLK may be applied or set to

master at any time; LRCK may only be applied or set to master while the PDN bit is set to 1.

Set the “Power Ctl 1” register (0x02) to 0x9E.

Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

4.10

Recommended Power-Down Sequence

To minimize audible pops when turning off or placing the DAC in standby,

Mute the DAC’s and PWM outputs.

Disable soft ramp and zero cross volume transitions.

Set the “Power Ctl 1” register (0x02) to 0x9F.

LRCK

SCLK

MS B

LS B

SDIN

HP/LINE OUTB

LS B

Le ft C h an n e l

R ight C h an n el

MS B

LS B MS B

Audio Word Length (AWL)

1/fs

HP/LINE OUTA

Figure 15. DSP Mode Format)

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