MPC5510 datasheet(33/54 Pages) FREESCALE

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Electrical Characteristics

MPC5510 Microcontroller Family Data Sheet, Rev. 2

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

2.9

FMPLL Electrical Characteristics

Table 14. FMPLL Electrical Specifications 1

1 V

DDSYN = 3.0V to 3.6 V, VSSSYN = 0 V, TA = TL to TH

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

System frequency2

-40 oC

≤ T

J ≤ 120

-40 oC

≤ T

J ≤ 145

2 The maximum value is without frequency modulation turned on. If frequency modulation is turned on, the maximum value

(average frequency) must be de-rated by the percentage of modulation enabled.

fsys

375

80000 3

66000

3 80 MHz is not available in the 176 pin package.

kHz

PLL Reference Frequency (output of predivider)

fpllref

410

MHz

VCO Frequency4

4 Optimum performance is achieved with the highest VCO frequency feasible based on the highest ERFD that results in the desired

PLL frequency.

fvco

192

500

MHz

PLL Frequency 5

-40 oC

≤ T

J ≤ 120

-40 oC

≤ T

J ≤ 145

5 The VCO frequency range is higher than the maximum allowable PLL frequency. The synthesizer control register 2’s enchanced

reduced frequency divider (FMPLL_SYNCR2[ERFD]) in enhanced operation mode must be programmed to divide the VCO

frequency within the PLL frequency range.

fpll

80 3

MHz

Loss of Reference Frequency 6

6 Loss of reference frequency is the reference frequency detected by the PLL which then transitions into self clocked mode.

fLOR

100

1000

kHz

Self Clocked Mode Frequency 7

7 Self clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f

LOR.

fSCM

MHz

PLL Lock Time 8

8 This specification applies to the period required for the PLL to relock after changing the enhanced multiplication factor divider

(EMFD) bits in the synthesizer control register 1 (SYNCR1) in enhanced operation mode.

tlpll

—750

μs

Frequency un-LOCK Range

fUL

– 4.0

4.0

% fsys

Frequency LOCK Range

fLCK

– 2.0

2.0

% fsys

CLKOUT Cycle-to-cycle Jitter,9, 10

9 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f

sys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage

for a given interval. CLKOUT divider set to divide-by-2.

10 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of C

jitter + Cmod.

Cjitter

– 5

% fclkout

Frequency Modulation Depth 1% Setting 11,12

(fsysMax must not be exceeded)

11 Modulation depth selected must not result in f

sys value greater than the fsys maximum specified value.

12 These depth ranges are obtained by filtering the raw cycle-to-cycle clock frequency data to eliminate the presence of the the

normal clock jitter riding on top of the FM waveform. The allowable modulation rates are 400 kHz to 1 MHz.

Cmod

0.5

%fsys

Frequency Modulation Depth 2% Setting 11,12

(fsysMax must not be exceeded)

Cmod

%fsys

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