8-BIT OPERATION TIMING

1

SCLK

CS

8

1

1

1

SDO

PENIRQ

S

SDI

ControlBits

S

ControlBits

HIGH: Disableor(EnableandNotTouched)

New

Definition

PENIRQ

LOW: EnableandTouched

7

6

5

7

6

5

4

3

2

1

0

8

1

1

8

SER/

DFR

PD1 PD0

SER/

DFR

PD1 PD0

n

n +1

n

n +1

HIGH: Disableor

(EnableandNotTouched)

LOW: EnableandTouched

Idle

Acquire Conv

Idle

Acquire Conv

Idle

New

Def

PENIRQ

1

SCLK

CS

8

1

SDO

PENIRQ

S

SDI

ControlBits

S

1

1

ControlBits

HIGH: Disableor(EnableandNotTouched)

LOW: EnableandTouched

7

6

5

7

6

5

4

4

3

2

1

0

8

1

SER/

DFR

PD1 PD0

SER/

DFR

PD1 PD0

n

n +1

n

n +1

HIGH: Disableor

(EnableandNotTouched)

LOW: EnableandTouched

Idle

Acquire Conv

Idle

Acquire

Conv

Idle

TSC2008

If the 8-bit ADC mode produces an acceptable result, then 16 SCLKs per cycle operation can also be used, as

shown in Figure 32. If SDO is released one-half SCLK cycle earlier (with the SDO adjusted option), the fastest

transfer (eight SCLKs per cycle) is achievable; see Figure 33.

Figure 32. Conversion Timing—8-Bit Mode, 16 SCLKs per Cycle, 8-Bit Bus Interface, without Adjusted

SDO Timing (TSC2046-Compatible)

Figure 33. Conversion Timing—8-Bit Mode, 8 SCLKs per Cycle, 8-Bit Bus Interface, with Adjusted SDO

Timing

Copyright © 2008, Texas Instruments Incorporated

Submit Documentation Feedback

25

Product Folder Link(s): TSC2008